[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Override PRERAM_CBMEM_CONSOLE_SIZE default value

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change and it was merged. ( https://review.coreboot.org/c/coreboot/+/34006 )

Change subject: soc/intel/cannonlake: Override PRERAM_CBMEM_CONSOLE_SIZE default value
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soc/intel/cannonlake: Override PRERAM_CBMEM_CONSOLE_SIZE default value

This patch increases PRERAM_CBMEM_CONSOLE_SIZE to fix
*** Pre-CBMEM romstage console overflowed, log truncated! ***
issue.

TEST=Verified on Hatch CML platform.

Change-Id: I2de4ca2f2001b304850c27df1b3c3b2c827fe25a
Signed-off-by: Subrata Banik 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34006
Tested-by: build bot (Jenkins) 
Reviewed-by: V Sowmya 
Reviewed-by: Spoorthi K
Reviewed-by: Nico Huber 
---
M src/soc/intel/cannonlake/Kconfig
1 file changed, 4 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, but someone else must approve
  V Sowmya: Looks good to me, approved
  Spoorthi K: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig
index d697620..5e405db 100644
--- a/src/soc/intel/cannonlake/Kconfig
+++ b/src/soc/intel/cannonlake/Kconfig
@@ -326,4 +326,8 @@
      This sets the Enable8254ClockGating UPD, which according to the FSP Integration
      guide needs to be disabled in order to boot SeaBIOS, but should otherwise be enabled.

+config PRERAM_CBMEM_CONSOLE_SIZE
+	hex
+	default 0xe00
+
 endif