Tim Wawrzynczak has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48847 )
Change subject: soc/intel/alderlake: Update CPU microcode patch base address/size ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48847/1/src/soc/intel/alderlake/fsp... File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48847/1/src/soc/intel/alderlake/fsp... PS1, Line 112:
What if FSP(UCODE loader) fails to load UCODE? […]
But this 2nd load can load different ucode than is available in FIT; that's the whole point of doing the 2nd load, isn't it? Until we enable the in-the-field ucode update, the ucode in FIT is RO, so this is how we ship install new ucode; it might be good to have some kind of indication from FSP (I guess that means parsing a new HOB) if the ucode update was successful or not, but that's probably going to be a bigger effort, I'll file a bug and CC you two on it.