[coreboot-gerrit] Change in coreboot[master]: soc/amd/stoneyridge: Move some SMI utility functions

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/42989 )

Change subject: soc/amd/stoneyridge: Move some SMI utility functions
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soc/amd/stoneyridge: Move some SMI utility functions

Change-Id: I4410772a8d3f2dedbb96601d87efb23b14e5f438
Signed-off-by: Kyösti Mälkki 
---
M src/soc/amd/stoneyridge/Makefile.inc
M src/soc/amd/stoneyridge/gpio.c
D src/soc/amd/stoneyridge/smi.c
M src/soc/amd/stoneyridge/smi_util.c
M src/soc/amd/stoneyridge/smihandler.c
5 files changed, 22 insertions(+), 33 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/42989/1

diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc
index 0d7b5d1..09320b2 100644
--- a/src/soc/amd/stoneyridge/Makefile.inc
+++ b/src/soc/amd/stoneyridge/Makefile.inc
@@ -64,7 +64,6 @@
 ramstage-y += pmutil.c
 ramstage-y += sata.c
 ramstage-y += memmap.c
-ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
 ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c
 ramstage-$(CONFIG_STONEYRIDGE_UART) += uart.c
 ramstage-y += usb.c
diff --git a/src/soc/amd/stoneyridge/gpio.c b/src/soc/amd/stoneyridge/gpio.c
index a595014..bd9d1b1 100644
--- a/src/soc/amd/stoneyridge/gpio.c
+++ b/src/soc/amd/stoneyridge/gpio.c
@@ -33,11 +33,6 @@
    { GPIO_69, GEVENT_17 },
 };

-void soc_route_sci(uint8_t event)
-{
-	smi_write8(SMI_SCI_MAP(event), event);
-}
-
 void soc_get_gpio_event_table(const struct soc_amd_event **table, size_t *items)
 {
    *table = gpio_event_table;
diff --git a/src/soc/amd/stoneyridge/smi.c b/src/soc/amd/stoneyridge/smi.c
deleted file mode 100644
index fb6d348..0000000
--- a/src/soc/amd/stoneyridge/smi.c
+++ /dev/null
@@ -1,20 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-
-/*
- * Utilities for SMM setup
- */
-
-#include <console/console.h>
-#include <cpu/x86/smm.h>
-#include <amdblocks/acpimmio.h>
-#include <soc/southbridge.h>
-#include <soc/smi.h>
-
-/** Set the EOS bit and enable SMI generation from southbridge */
-void global_smi_enable(void)
-{
-	uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
-	reg &= ~SMITRG0_SMIENB;	/* Enable SMI generation */
-	reg |= SMITRG0_EOS;	/* Set EOS bit */
-	smi_write32(SMI_REG_SMITRIG0, reg);
-}
diff --git a/src/soc/amd/stoneyridge/smi_util.c b/src/soc/amd/stoneyridge/smi_util.c
index 2c5085b..b65bfc0 100644
--- a/src/soc/amd/stoneyridge/smi_util.c
+++ b/src/soc/amd/stoneyridge/smi_util.c
@@ -5,6 +5,7 @@
  */

#include <console/console.h>
+#include <cpu/x86/smm.h>
 #include <soc/southbridge.h>
 #include <soc/smi.h>
 #include <amdblocks/acpimmio.h>
@@ -56,6 +57,27 @@
    smi_write32(SMI_REG_SMITRIG0, reg32);
 }

+/** Set the EOS bit and enable SMI generation from southbridge */
+void global_smi_enable(void)
+{
+	uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
+	reg &= ~SMITRG0_SMIENB;	/* Enable SMI generation */
+	reg |= SMITRG0_EOS;	/* Set EOS bit */
+	smi_write32(SMI_REG_SMITRIG0, reg);
+}
+
+void southbridge_smi_set_eos(void)
+{
+	uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
+	reg |= SMITRG0_EOS;
+	smi_write32(SMI_REG_SMITRIG0, reg);
+}
+
+void soc_route_sci(uint8_t event)
+{
+	smi_write8(SMI_SCI_MAP(event), event);
+}
+
 /**
  * Configure generation of SCIs.
  */
diff --git a/src/soc/amd/stoneyridge/smihandler.c b/src/soc/amd/stoneyridge/smihandler.c
index be55458..a36ab73 100644
--- a/src/soc/amd/stoneyridge/smihandler.c
+++ b/src/soc/amd/stoneyridge/smihandler.c
@@ -287,10 +287,3 @@
    if (smi_src & SMI_STATUS_SRC_4)
    	process_smi_sources(SMI_REG_SMISTS4);
 }
-
-void southbridge_smi_set_eos(void)
-{
-	uint32_t reg = smi_read32(SMI_REG_SMITRIG0);
-	reg |= SMITRG0_EOS;
-	smi_write32(SMI_REG_SMITRIG0, reg);
-}