14 Jan
2019
14 Jan
'19
10:55 a.m.
Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/25603 )
Change subject: nb/intel/i945: Put stage cache in TSEG ......................................................................
Patch Set 37:
(1 comment)
https://review.coreboot.org/#/c/25603/37//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/25603/37//COMMIT_MSG@16 PS37, Line 16: So was resume broken, or is it some preparation work?
--
To view, visit https://review.coreboot.org/c/coreboot/+/25603
To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I447815bb0acf5f8e53834b74785d496f9d4df1da
Gerrit-Change-Number: 25603
Gerrit-PatchSet: 37
Gerrit-Owner: Arthur Heymans arthur@aheymans.xyz
Gerrit-Reviewer: Arthur Heymans arthur@aheymans.xyz
Gerrit-Reviewer: HAOUAS Elyes ehaouas@noos.fr
Gerrit-Reviewer: Martin Roth martinroth@google.com
Gerrit-Reviewer: Patrick Georgi pgeorgi@google.com
Gerrit-Reviewer: Patrick Rudolph siro@das-labor.org
Gerrit-Reviewer: Paul Menzel paulepanter@users.sourceforge.net
Gerrit-Reviewer: Stefan Reinauer stefan.reinauer@coreboot.org
Gerrit-Reviewer: build bot (Jenkins) no-reply@coreboot.org
Gerrit-Comment-Date: Mon, 14 Jan 2019 10:55:49 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Gerrit-MessageType: comment