Maulik V Vaghela has uploaded this change for review. ( https://review.coreboot.org/27087
Change subject: Documentation/Intel: Add common code design document ......................................................................
Documentation/Intel: Add common code design document
Add common code design document support Intel SoCs such as Skylake, Cannonlake and Apollolake onwards.
Documented items: *Introduction *Design Principle *Common code development and status *Common code structure *Benifits
Change-Id: I5ade390cfb41c72f812d5cc4e00e67a5964721de Signed-off-by: Maulik V Vaghela maulik.v.vaghela@intel.com --- A Documentation/Intel/code_development_model/Code_development_model.md A Documentation/Intel/code_development_model/coreboot_common_code_design.png 2 files changed, 93 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/27087/1
diff --git a/Documentation/Intel/code_development_model/Code_development_model.md b/Documentation/Intel/code_development_model/Code_development_model.md new file mode 100644 index 0000000..9e03404 --- /dev/null +++ b/Documentation/Intel/code_development_model/Code_development_model.md @@ -0,0 +1,93 @@ +# Intel common code development strategy + +## Introduction + +This document captures the development strategy for Intel SOC code development +of coreboot. As Intel keeps advancing hardware development and as new generation +SoC is developed, we also need to add support for these SOCs into coreboot. + +We add this support inside soc/intel/<soc name> folder. This folder contains all +the files which are related to particular SoC. + +There might be still common code lying across some SoCs but this document +captures our efforts on putting maximum code as a common code across all the +SoCs and what can't be put into common code due to vulnerability to change in +future. + +## Design principal + +Any Intel coreboot projects can be split into 3 parts: +1. SoC = It contains all the IP/component initialization code +2. Mainboard = OxM boards, build based on underlying SoC support +3. FSP = Intel firmware support package to abstract all restricted SoC registers +from open source world. + +Historically, we used to copy "X-1" generation SoC code into "X" new SoC while +adding support for new SoC at open source. This results in having same +initialization code in both projects. This method increases redundant code +across multiple SoCs and also it increases overhead for reviewers and +maintainers also. + +To solve this issue, we started following converged IP model. Intel Silicon team +uses same IP/controller across various Intel SoCs. For example, LPSS based UART +controller is same across all SoC products. Thus "converged IP model" was +propsed as firmware development model to create common IP library across +multiple SoC products and creating BIOS/firmware for future SoC will be much +simpler by just using those APIs based on certain configurations. + +## Common Code Development and Status + +Intel's proposed "converged IP model" is also called as common code phase 1.0, +and it has reduced number of lines in single SoC folder by over 50%. + +We continue to analyze code which can still be moved to common and try to reduce +footprint of the code lying in each SoC folder. With current Intel SoC +development model, PCH is emerged as a separate component for big core SoCs. +Intel hardware design started following model where same PCH is used across +multiple SoCs, which gives us an opportunity to make code more common across +SoCs which uses same PCH. As part of this idea, common code phase 1.1 has +emerged and we'll try to create PCH binding for SoCs and thus further reducing +footprint of SoC code. + +Common code phase 1.1 will make code more modular for big core SoCs but there +is still some scope to make code flow common across small core and big core +SoCs. We will take it up as a part of common code phase 2.0 and make code flow +common across small core and big core SoCs which will help us to reduce the +footprint of code as well as have a unified code flow for all Intel SoCs. + +Here's a table which summarizes common code phase and status: +|-----------------------------------------------------------------------------| +| Common code | summary | status | +| phase | | | +|-----------------------------------------------------------------------------| +| 1.0 |follow "converged IP model" as described | Patches in | +| |above and create common IP code which can be | Review | +| |used across multiple SoCs | | +|-----------------------------------------------------------------------------| +| 1.1 |Create PCH binding for big core SoCs. SoCs |In development| +| |having same PCH can use common code. |Base patch | +| | |merged | +|-----------------------------------------------------------------------------| +| 2.0 |Use common stage files (bootblock, romstage) |In development| +| |across small core and big core SoCs. This | | +| |will unify flow for all Intel SoCs. | | +|-----------------------------------------------------------------------------| + +## Common code structure + +Code design after common code in coreboot will look like as follow: + +![alt text][coreboot_common_code_design] +[coreboot_common_code_design]: coreboot_common_code_design.png "coreboot common code structure" + +There will be still some files left in each SOC folder and we may copy it across +SOC as a base but these files are vulnerable to change as development continues. + +## Benefits + +1. coreboot will have less redundant code which is spread across multiple SOC +as of now. +2. Design will be easy to understand by community since code flow will be same +for all the SoCs. +3. Since we are aligning software code design with hardware philosophy, it'll +be easier to map why each change was done in code/SOC. diff --git a/Documentation/Intel/code_development_model/coreboot_common_code_design.png b/Documentation/Intel/code_development_model/coreboot_common_code_design.png new file mode 100644 index 0000000..b5370ef --- /dev/null +++ b/Documentation/Intel/code_development_model/coreboot_common_code_design.png Binary files differ