[coreboot-gerrit] Change in coreboot[master]: soc/tigerlake: Correct FSP log interface for JSL

[Ronak Kanabar (Code Review)]

Ronak Kanabar has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/39280 )

Change subject: soc/tigerlake: Correct FSP log interface for JSL
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soc/tigerlake: Correct FSP log interface for JSL

Set DEBUG_INTERFACE_TRACEHUB as default and select correct UART.
DEBUG_INTERFACE_UART: Legacy UART
DEBUG_INTERFACE_SERIAL_IO: PCH UART

BUG=None
TEST=boot jslrvp board with Debug FSP and check FSP uart log
Signed-off-by: Ronak Kanabar

Change-Id: I7be7f93082f9c64c1c45963d70ee2e3b3d29986a
---
M src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
1 file changed, 1 insertion(+), 1 deletion(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/39280/1

diff --git a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
index 56124f4..3dc87ee 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params_jsl.c
@@ -70,7 +70,7 @@
    /* Set CPU Ratio */
    m_cfg->CpuRatio = 0;
    m_cfg->PcdDebugInterfaceFlags = CONFIG(DRIVERS_UART_8250IO) ?
-			DEBUG_INTERFACE_UART : DEBUG_INTERFACE_TRACEHUB;
+			DEBUG_INTERFACE_UART : DEBUG_INTERFACE_SERIAL_IO;

/* Change VmxEnable UPD value according to ENABLE_VMX Kconfig */
    m_cfg->VmxEnable = CONFIG(ENABLE_VMX);