[coreboot-gerrit] Change in coreboot[master]: ish: enable for Sarien

[Li1 Feng (Code Review)]

Li1 Feng has uploaded this change for review. ( https://review.coreboot.org/29493

Change subject: ish: enable for Sarien
......................................................................

ish: enable for Sarien

WIP: not merge
C12/C13 is configured for ISH UART1
Signed-off-by: li feng

Change-Id: Ibdb9eae3bb5e8beef3b6727ef8aae88d16893666
---
M src/mainboard/google/sarien/variants/sarien/devicetree.cb
M src/mainboard/google/sarien/variants/sarien/gpio.c
2 files changed, 3 insertions(+), 3 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/29493/1

diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
index 1360b3f..55c2d11 100644
--- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb
+++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb
@@ -106,6 +106,7 @@
    	device pci 02.0 on  end # Integrated Graphics Device
    	device pci 04.0 on  end # SA Thermal device
    	device pci 12.0 on  end # Thermal Subsystem
+		device pci 13.0 on  end # ISH
    	device pci 12.5 off end # UFS SCS
    	device pci 12.6 off end # GSPI #2
    	device pci 14.0 on  end # USB xHCI
diff --git a/src/mainboard/google/sarien/variants/sarien/gpio.c b/src/mainboard/google/sarien/variants/sarien/gpio.c
index 690af1f..95e395f 100644
--- a/src/mainboard/google/sarien/variants/sarien/gpio.c
+++ b/src/mainboard/google/sarien/variants/sarien/gpio.c
@@ -82,9 +82,8 @@
 /* UART0_TXD */		PAD_NC(GPP_C9, NONE),
 /* UART0_RTS# */	PAD_CFG_GPI(GPP_C10, NONE, DEEP), /* TYPEC_CON_SEL1 */
 /* UART0_CTS# */	PAD_CFG_GPI(GPP_C11, NONE, DEEP), /* TYPEC_CON_SEL2 */
-/* UART1_RXD */         PAD_CFG_GPI_SCI_LOW(GPP_C12, NONE, DEEP,
-				    EDGE_SINGLE), /* SIO_EXT_WAKE# */
-/* UART1_TXD */		PAD_NC(GPP_C13, NONE),
+/* UART1_RXD */     PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1),
+/* UART1_TXD */		PAD_CFG_NF(GPP_C13, NONE, DEEP, NF1),
 /* UART1_RTS# */	PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* LCD_CBL_DET# */
 /* UART1_CTS# */	PAD_NC(GPP_C15, NONE),
 /* I2C0_SDA */		PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TS_I2C_SDA */