Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Rizwan Qureshi, Justin TerAvest, Angel Pons, Subrata Banik, Patrick Rudolph, Karthik Ramasubramanian,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/39823
to look at the new patch set (#3).
Change subject: soc/intel/jasperlake: Add Jasper Lake SoC support ......................................................................
soc/intel/jasperlake: Add Jasper Lake SoC support
This is a copy patch from Tiger Lake SoC code.
The only changes done on top of copy is changing below configs: 1. SOC_INTEL_TIGERLAKE -> SOC_INTEL_TIGERLAKE_COPY 2. SOC_INTEL_JASPERLAKE -> SOC_INTEL_JASPERLAKE_COPY 3. SOC_INTEL_TIGERLAKE_BASE -> SOC_INTEL_TIGERLAKE_BASE_COPY
We started with initial assumption that JSL and TGL can co-exist. But now we see the SoC code in Tiger Lake is relying on too many compile-time directives to make two SoCs co-exist.
The split of JSL and TGL SoC code is planned as below:
1. Copy Tiger Lake SoC code as is, and change SoC Kconfig to avoid conflicts with current mainboard builds.
2. Clean up TGL code out of copy patch done in step 1. Make it JSL only code. The SoC config still kept as SOC_INTEL_JASPERLAKE_COPY.
3. Change JSL SOC Kconfig from SOC_INTEL_JASPERLAKE_COPY to SOC_INTEL_JASPERLAKE, dedede and jasperlake_rvp boards can bind to SoC code from soc/intel/jasperlake. This step establishes Jasper Lake as a separate SoC.
4. Clean up current JSL code from TGL code. This step establishes Tiger Lake as a separate SoC.
BUG=b:150217037
Change-Id: I9c33f478a2f8ed5e2d8e7815821d13044d35d388 Signed-off-by: Aamir Bohra aamir.bohra@intel.com --- A src/soc/intel/jasperlake/Kconfig A src/soc/intel/jasperlake/Makefile.inc A src/soc/intel/jasperlake/acpi.c A src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl A src/soc/intel/jasperlake/acpi/gpio.asl A src/soc/intel/jasperlake/acpi/gpio_op.asl A src/soc/intel/jasperlake/acpi/ipu.asl A src/soc/intel/jasperlake/acpi/ish.asl A src/soc/intel/jasperlake/acpi/pch_glan.asl A src/soc/intel/jasperlake/acpi/pch_hda.asl A src/soc/intel/jasperlake/acpi/pci_irqs.asl A src/soc/intel/jasperlake/acpi/pci_irqs_jsl.asl A src/soc/intel/jasperlake/acpi/pci_irqs_tgl.asl A src/soc/intel/jasperlake/acpi/pcie.asl A src/soc/intel/jasperlake/acpi/platform.asl A src/soc/intel/jasperlake/acpi/pmc.asl A src/soc/intel/jasperlake/acpi/scs.asl A src/soc/intel/jasperlake/acpi/serialio.asl A src/soc/intel/jasperlake/acpi/smbus.asl A src/soc/intel/jasperlake/acpi/southbridge.asl A src/soc/intel/jasperlake/acpi/xhci.asl A src/soc/intel/jasperlake/acpi/xhci_jsl.asl A src/soc/intel/jasperlake/acpi/xhci_tgl.asl A src/soc/intel/jasperlake/bootblock/bootblock.c A src/soc/intel/jasperlake/bootblock/cpu.c A src/soc/intel/jasperlake/bootblock/pch.c A src/soc/intel/jasperlake/bootblock/report_platform.c A src/soc/intel/jasperlake/chip.c A src/soc/intel/jasperlake/chip.h A src/soc/intel/jasperlake/cpu.c A src/soc/intel/jasperlake/elog.c A src/soc/intel/jasperlake/espi.c A src/soc/intel/jasperlake/finalize.c A src/soc/intel/jasperlake/fsp_params_jsl.c A src/soc/intel/jasperlake/fsp_params_tgl.c A src/soc/intel/jasperlake/gpio_jsl.c A src/soc/intel/jasperlake/gpio_tgl.c A src/soc/intel/jasperlake/graphics.c A src/soc/intel/jasperlake/gspi.c A src/soc/intel/jasperlake/i2c.c A src/soc/intel/jasperlake/include/soc/bootblock.h A src/soc/intel/jasperlake/include/soc/cpu.h A src/soc/intel/jasperlake/include/soc/espi.h A src/soc/intel/jasperlake/include/soc/gpe.h A src/soc/intel/jasperlake/include/soc/gpio.h A src/soc/intel/jasperlake/include/soc/gpio_defs.h A src/soc/intel/jasperlake/include/soc/gpio_defs_jsl.h A src/soc/intel/jasperlake/include/soc/gpio_defs_tgl.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs_jsl.h A src/soc/intel/jasperlake/include/soc/gpio_soc_defs_tgl.h A src/soc/intel/jasperlake/include/soc/iomap.h A src/soc/intel/jasperlake/include/soc/irq.h A src/soc/intel/jasperlake/include/soc/irq_jsl.h A src/soc/intel/jasperlake/include/soc/irq_tgl.h A src/soc/intel/jasperlake/include/soc/itss.h A src/soc/intel/jasperlake/include/soc/me.h A src/soc/intel/jasperlake/include/soc/meminit_jsl.h A src/soc/intel/jasperlake/include/soc/meminit_tgl.h A src/soc/intel/jasperlake/include/soc/msr.h A src/soc/intel/jasperlake/include/soc/nvs.h A src/soc/intel/jasperlake/include/soc/p2sb.h A src/soc/intel/jasperlake/include/soc/pch.h A src/soc/intel/jasperlake/include/soc/pci_devs.h A src/soc/intel/jasperlake/include/soc/pcr_ids.h A src/soc/intel/jasperlake/include/soc/pm.h A src/soc/intel/jasperlake/include/soc/pmc.h A src/soc/intel/jasperlake/include/soc/ramstage.h A src/soc/intel/jasperlake/include/soc/romstage.h A src/soc/intel/jasperlake/include/soc/serialio.h A src/soc/intel/jasperlake/include/soc/smbus.h A src/soc/intel/jasperlake/include/soc/soc_chip.h A src/soc/intel/jasperlake/include/soc/systemagent.h A src/soc/intel/jasperlake/include/soc/usb.h A src/soc/intel/jasperlake/lockdown.c A src/soc/intel/jasperlake/meminit_jsl.c A src/soc/intel/jasperlake/meminit_tgl.c A src/soc/intel/jasperlake/p2sb.c A src/soc/intel/jasperlake/pmc.c A src/soc/intel/jasperlake/pmutil.c A src/soc/intel/jasperlake/reset.c A src/soc/intel/jasperlake/romstage/Makefile.inc A src/soc/intel/jasperlake/romstage/fsp_params_jsl.c A src/soc/intel/jasperlake/romstage/fsp_params_tgl.c A src/soc/intel/jasperlake/romstage/pch.c A src/soc/intel/jasperlake/romstage/romstage.c A src/soc/intel/jasperlake/romstage/systemagent.c A src/soc/intel/jasperlake/sd.c A src/soc/intel/jasperlake/smihandler.c A src/soc/intel/jasperlake/smmrelocate.c A src/soc/intel/jasperlake/spi.c A src/soc/intel/jasperlake/systemagent.c A src/soc/intel/jasperlake/uart.c 93 files changed, 10,462 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/39823/3