EricR Lai has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config
......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/rom...
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/rom...
PS1, Line 48: PcieRp[i].clksrc
can u please help me to understand, how this variable will get its value ?
I hope it can use like this in devicetree. Need to try though...
register "PcieRp[6]" = "{
"enabled" = "1",
"clksrc" = "3",
"clkreq" = "4",
}
--
To view, visit
https://review.coreboot.org/c/coreboot/+/48340
To unsubscribe, or for help writing mail filters, visit
https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b
Gerrit-Change-Number: 48340
Gerrit-PatchSet: 2
Gerrit-Owner: EricR Lai
ericr_lai@compal.corp-partner.google.com
Gerrit-Reviewer: Furquan Shaikh
furquan@google.com
Gerrit-Reviewer: Patrick Rudolph
siro@das-labor.org
Gerrit-Reviewer: Subrata Banik
subrata.banik@intel.com
Gerrit-Reviewer: Tim Wawrzynczak
twawrzynczak@chromium.org
Gerrit-Reviewer: build bot (Jenkins)
no-reply@coreboot.org
Gerrit-Comment-Date: Sat, 05 Dec 2020 09:16:07 +0000
Gerrit-HasComments: Yes
Gerrit-Has-Labels: No
Comment-In-Reply-To: Subrata Banik
subrata.banik@intel.com
Gerrit-MessageType: comment