[coreboot-gerrit] [XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIF and PMIC driver support

[Yidi Lin (Code Review)]

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu.

Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85126?usp=email )

Change subject: soc/mediatek/mt8196: Add PMIF and PMIC driver support
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Patch Set 14:

(1 comment)

File src/soc/mediatek/mt8196/pmif_spmi.c:

https://review.coreboot.org/c/coreboot/+/85126/comment/87207f0f_9e793842?usp... :
PS14, Line 164: 	write32p(SPMI_SCL_OFFSET4_ADDR, 0x100);
              : 	write32p(SPMI_SCL_OFFSET8_ADDR, 0xC0);
              : 	write32p(SPMI_SCL_OFFSET4_ADDR, 0x800);
              : 	write32p(SPMI_SCL_OFFSET8_ADDR, 0x600);
              : 	/* SPMI_P 14mA */
              : 	write32p(SPMI_SCL_OFFSET4_ADDR, 0x6000);
              : 	write32p(SPMI_SCL_OFFSET8_ADDR, 0x1000);
              : 	write32p(SPMI_SCL_OFFSET4_ADDR, 0x30000);
              : 	write32p(SPMI_SCL_OFFSET8_ADDR, 0x8000);
What about
```
gpio_set_driving(GPIO(SPMI_M_SCL), GPIO_DRV_10_MA);
gpio_set_driving(GPIO(SPMI_M_SDA), GPIO_DRV_10_MA);
gpio_set_driving(GPIO(SPMI_P_SCL), GPIO_DRV_14_MA);
gpio_set_driving(GPIO(SPMI_P_SDA), GPIO_DRV_14_MA);
```
I think they should be identical. You can update the address `IOCFG_LM2_BASE` to verify the change. (0x4 is the set register and 0x8 is the clear register according to GPIO register definition)