Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74809 )
Change subject: soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses ......................................................................
soc/amd/stoneyridge/acpi/sb_pci0_fch: report correct number of PCI buses
This ports back commit commit d75ee46d3ce6 ("soc/amd/picasso/acpi: Change PCI0 BAR window") to Stoneyridge so that the correct end of the non-fixed MMIO region gets reported in PCI0's _CRS method.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I19153947cbb1b1b684291765eb1902caac65b9ec --- M src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl 1 file changed, 16 insertions(+), 9 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/74809/1
diff --git a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl index dad8aaa..a4903e9 100644 --- a/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl +++ b/src/soc/amd/stoneyridge/acpi/sb_pci0_fch.asl @@ -98,16 +98,9 @@ CreateDWordField(CRES, ^MMIO._BAS, MM1B) CreateDWordField(CRES, ^MMIO._LEN, MM1L)
- /* - * Declare memory between TOM1 and 4GB as available - * for PCI MMIO. - * Use ShiftLeft to avoid 64bit constant (for XP). - * This will work even if the OS does 32bit arithmetic, as - * 32bit (0x00000000 - TOM1) will wrap and give the same - * result as 64bit (0x100000000 - TOM1). - */ + /* Declare memory between TOM1 and MMCONF as available for PCI MMIO. */ MM1B = TOM1 - Local0 = 0x10000000 << 4 + Local0 = CONFIG_ECAM_MMCONF_BASE_ADDRESS Local0 -= TOM1 MM1L = Local0