[coreboot-gerrit] Change in coreboot[master]: soc/intel/alderlake: Update UART0 GPIO as per latest schematics

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/47847 )

Change subject: soc/intel/alderlake: Update UART0 GPIO as per latest schematics
......................................................................

soc/intel/alderlake: Update UART0 GPIO as per latest schematics

UART0_RX: C8 -> H10
UART0_TX: C9 -> H11

GPIO PIN Mode: NF1 -> NF2

Change-Id: I7a193b67e22258ff600679f27955a37480ed3f0d
Signed-off-by: Subrata Banik 
---
M src/soc/intel/alderlake/uart.c
1 file changed, 2 insertions(+), 2 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/47847/1

diff --git a/src/soc/intel/alderlake/uart.c b/src/soc/intel/alderlake/uart.c
index cdbf8ec..a3bdc4a 100644
--- a/src/soc/intel/alderlake/uart.c
+++ b/src/soc/intel/alderlake/uart.c
@@ -21,8 +21,8 @@
    {
    	.console_index = 0,
    	.gpios = {
-			PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */
-			PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */
+			PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0 RX */
+			PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0 TX */
    	},
    },
    {