Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/37451 )
Change subject: [WIP] hudson_lpc_port80 ......................................................................
[WIP] hudson_lpc_port80
Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- M src/mainboard/amd/bettong/romstage.c M src/mainboard/amd/db-ft3b-lc/romstage.c M src/mainboard/amd/lamar/romstage.c M src/mainboard/amd/olivehill/romstage.c M src/mainboard/amd/olivehillplus/romstage.c M src/mainboard/amd/parmer/romstage.c M src/mainboard/amd/thatcher/romstage.c M src/mainboard/asrock/imb-a180/romstage.c M src/mainboard/asus/am1i-a/romstage.c M src/mainboard/asus/f2a85-m/romstage.c M src/mainboard/bap/ode_e20XX/romstage.c M src/mainboard/bap/ode_e21XX/romstage.c M src/mainboard/biostar/a68n_5200/romstage.c M src/mainboard/biostar/am1ml/romstage.c M src/mainboard/gizmosphere/gizmo2/romstage.c M src/mainboard/hp/abm/romstage.c M src/mainboard/hp/pavilion_m6_1035dx/romstage.c M src/mainboard/lenovo/g505s/romstage.c M src/mainboard/msi/ms7721/romstage.c M src/mainboard/pcengines/apu2/bootblock.c M src/southbridge/amd/agesa/hudson/bootblock.c 21 files changed, 5 insertions(+), 46 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/51/37451/1
diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index c9a257c..58430dc 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -29,8 +29,6 @@ { u32 val;
- hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30);
diff --git a/src/mainboard/amd/db-ft3b-lc/romstage.c b/src/mainboard/amd/db-ft3b-lc/romstage.c index 475431e..a0c6b8d 100644 --- a/src/mainboard/amd/db-ft3b-lc/romstage.c +++ b/src/mainboard/amd/db-ft3b-lc/romstage.c @@ -37,8 +37,6 @@ outb(0xD2, 0xcd6); outb(0x00, 0xcd7);
- hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30);
diff --git a/src/mainboard/amd/lamar/romstage.c b/src/mainboard/amd/lamar/romstage.c index 4dde4e2..7f37990 100644 --- a/src/mainboard/amd/lamar/romstage.c +++ b/src/mainboard/amd/lamar/romstage.c @@ -48,8 +48,6 @@ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x28) |= 1 << 18; /* 24Mhz */ *(volatile u32 *) (AMD_SB_ACPI_MMIO_ADDR + 0xE00 + 0x40) &= ~(1 << 2); /* 24Mhz */
- hudson_lpc_port80(); - if (!cpu_init_detectedx) { post_code(0x30); f81216h_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE, MODE_7777); diff --git a/src/mainboard/amd/olivehill/romstage.c b/src/mainboard/amd/olivehill/romstage.c index 9a28f98..122bb19 100644 --- a/src/mainboard/amd/olivehill/romstage.c +++ b/src/mainboard/amd/olivehill/romstage.c @@ -41,8 +41,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* On Larne, after LpcClkDrvSth is set, it needs some time to be stable, because of the buffer ICS551M */ for (i = 0; i < 200000; i++) val = inb(0xcd6); diff --git a/src/mainboard/amd/olivehillplus/romstage.c b/src/mainboard/amd/olivehillplus/romstage.c index bb80687..c04aafe 100644 --- a/src/mainboard/amd/olivehillplus/romstage.c +++ b/src/mainboard/amd/olivehillplus/romstage.c @@ -37,8 +37,6 @@ outb(0xD2, 0xcd6); outb(0x00, 0xcd7);
- hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30);
diff --git a/src/mainboard/amd/parmer/romstage.c b/src/mainboard/amd/parmer/romstage.c index 48aee89..6366c4e 100644 --- a/src/mainboard/amd/parmer/romstage.c +++ b/src/mainboard/amd/parmer/romstage.c @@ -19,8 +19,6 @@
void board_BeforeAgesa(struct sysinfo *cb) { - hudson_lpc_port80(); - pci_devfn_t dev = PCI_DEV(0, 0x14, 3);
/* For serial port option, plug-in card on LPC. */ diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 1d89e4d..5678021 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -31,7 +31,6 @@
/* Set LPC decode enables. */ dev = PCI_DEV(0, 0x14, 3); - hudson_lpc_port80();
byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ diff --git a/src/mainboard/asrock/imb-a180/romstage.c b/src/mainboard/asrock/imb-a180/romstage.c index ce5e064..5b9a226 100644 --- a/src/mainboard/asrock/imb-a180/romstage.c +++ b/src/mainboard/asrock/imb-a180/romstage.c @@ -35,8 +35,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); diff --git a/src/mainboard/asus/am1i-a/romstage.c b/src/mainboard/asus/am1i-a/romstage.c index 5e1218a..fff760b 100644 --- a/src/mainboard/asus/am1i-a/romstage.c +++ b/src/mainboard/asus/am1i-a/romstage.c @@ -144,8 +144,6 @@ pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); pci_write_config32(dev2, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); diff --git a/src/mainboard/asus/f2a85-m/romstage.c b/src/mainboard/asus/f2a85-m/romstage.c index d5acdb5..8a48e00 100644 --- a/src/mainboard/asus/f2a85-m/romstage.c +++ b/src/mainboard/asus/f2a85-m/romstage.c @@ -68,11 +68,6 @@ u8 byte; pci_devfn_t dev;
- if (CONFIG(POST_DEVICE_PCI_PCIE)) - hudson_pci_port80(); - else if (CONFIG(POST_DEVICE_LPC)) - hudson_lpc_port80(); - /* enable SIO LPC decode */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x48); diff --git a/src/mainboard/bap/ode_e20XX/romstage.c b/src/mainboard/bap/ode_e20XX/romstage.c index ef7a7fb..505de38 100644 --- a/src/mainboard/bap/ode_e20XX/romstage.c +++ b/src/mainboard/bap/ode_e20XX/romstage.c @@ -36,7 +36,5 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index e58f875..de39f18 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -41,8 +41,6 @@ outb(0xD2, 0xcd6); outb(0x00, 0xcd7);
- hudson_lpc_port80(); - if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); fintek_enable_serial(SERIAL_DEV1, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/biostar/a68n_5200/romstage.c b/src/mainboard/biostar/a68n_5200/romstage.c index ddcf4d0..5d210fa 100644 --- a/src/mainboard/biostar/a68n_5200/romstage.c +++ b/src/mainboard/biostar/a68n_5200/romstage.c @@ -58,12 +58,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- if (CONFIG(POST_DEVICE_PCI_PCIE)) - hudson_pci_port80(); - - if (CONFIG(POST_DEVICE_LPC)) - hudson_lpc_port80(); - /* enable SIO LPC decode */ byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ diff --git a/src/mainboard/biostar/am1ml/romstage.c b/src/mainboard/biostar/am1ml/romstage.c index c83a865..6c1581b 100644 --- a/src/mainboard/biostar/am1ml/romstage.c +++ b/src/mainboard/biostar/am1ml/romstage.c @@ -89,8 +89,6 @@ pci_devfn_t dev2 = PCI_DEV(0, 0x14, 3); pci_write_config32(dev2, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* Enable the AcpiMmio space */ outb(0x24, 0xcd6); outb(0x1, 0xcd7); diff --git a/src/mainboard/gizmosphere/gizmo2/romstage.c b/src/mainboard/gizmosphere/gizmo2/romstage.c index c656347..4676199 100644 --- a/src/mainboard/gizmosphere/gizmo2/romstage.c +++ b/src/mainboard/gizmosphere/gizmo2/romstage.c @@ -24,8 +24,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. diff --git a/src/mainboard/hp/abm/romstage.c b/src/mainboard/hp/abm/romstage.c index 2cc8d1b..d7322c9 100644 --- a/src/mainboard/hp/abm/romstage.c +++ b/src/mainboard/hp/abm/romstage.c @@ -32,8 +32,6 @@ pci_devfn_t dev = PCI_DEV(0, 0x14, 3); pci_write_config32(dev, 0x44, 0xff03ffd5);
- hudson_lpc_port80(); - /* In Hudson RRG, PMIOxD2[5:4] is "Drive strength control for * LpcClk[1:0]". To be consistent with Parmer, setting to 4mA * even though the register is not documented in the Kabini BKDG. diff --git a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c index c05b87a..0395566 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/romstage.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/romstage.c @@ -18,5 +18,4 @@
void board_BeforeAgesa(struct sysinfo *cb) { - hudson_lpc_port80(); } diff --git a/src/mainboard/lenovo/g505s/romstage.c b/src/mainboard/lenovo/g505s/romstage.c index c05b87a..0395566 100644 --- a/src/mainboard/lenovo/g505s/romstage.c +++ b/src/mainboard/lenovo/g505s/romstage.c @@ -18,5 +18,4 @@
void board_BeforeAgesa(struct sysinfo *cb) { - hudson_lpc_port80(); } diff --git a/src/mainboard/msi/ms7721/romstage.c b/src/mainboard/msi/ms7721/romstage.c index 0266eff..ebb875d 100644 --- a/src/mainboard/msi/ms7721/romstage.c +++ b/src/mainboard/msi/ms7721/romstage.c @@ -117,11 +117,6 @@ u8 byte; pci_devfn_t dev;
- if (CONFIG(POST_DEVICE_PCI_PCIE)) - hudson_pci_port80(); - else if (CONFIG(POST_DEVICE_LPC)) - hudson_lpc_port80(); - /* enable SIO LPC decode */ dev = PCI_DEV(0, 0x14, 3); byte = pci_read_config8(dev, 0x48); diff --git a/src/mainboard/pcengines/apu2/bootblock.c b/src/mainboard/pcengines/apu2/bootblock.c index 8318f39..7a5d84e 100644 --- a/src/mainboard/pcengines/apu2/bootblock.c +++ b/src/mainboard/pcengines/apu2/bootblock.c @@ -23,7 +23,6 @@
void bootblock_mainboard_early_init(void) { - hudson_lpc_port80(); hudson_clk_output_48Mhz();
/* COM2 on apu5 is reserved so only COM1 should be supported */ diff --git a/src/southbridge/amd/agesa/hudson/bootblock.c b/src/southbridge/amd/agesa/hudson/bootblock.c index 97e8803..e3e055e 100644 --- a/src/southbridge/amd/agesa/hudson/bootblock.c +++ b/src/southbridge/amd/agesa/hudson/bootblock.c @@ -77,6 +77,11 @@ hudson_lpc_decode(); enable_acpimmio_decode_pm24();
+ if (CONFIG(POST_DEVICE_PCI_PCIE)) + hudson_pci_port80(); + else if (CONFIG(POST_DEVICE_LPC)) + hudson_lpc_port80(); + dev = PCI_DEV(0, 0x14, 3); data = pci_read_config32(dev, LPC_IO_OR_MEM_DECODE_ENABLE); /* enable 0x2e/0x4e IO decoding for SuperIO */