Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/29252
Change subject: src: Replace common MSR addresses with macros ......................................................................
src: Replace common MSR addresses with macros
Change-Id: I9fba67be12483ea5e12ccd34c648735d409bc8b0 Signed-off-by: Elyes HAOUAS ehaouas@noos.fr --- M src/cpu/amd/family_10h-family_15h/fidvid.c M src/cpu/amd/microcode/microcode.c M src/cpu/x86/lapic/boot_cpu.c M src/cpu/x86/smm/smmhandler.S M src/include/cpu/x86/msr.h M src/northbridge/amd/amdht/AsPsDefs.h M src/northbridge/amd/amdht/h3finit.c M src/northbridge/amd/amdmct/mct_ddr3/mct_d.c M src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c 9 files changed, 12 insertions(+), 21 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/29252/1
diff --git a/src/cpu/amd/family_10h-family_15h/fidvid.c b/src/cpu/amd/family_10h-family_15h/fidvid.c index 428924d..4846825 100644 --- a/src/cpu/amd/family_10h-family_15h/fidvid.c +++ b/src/cpu/amd/family_10h-family_15h/fidvid.c @@ -89,6 +89,7 @@
*/
+#include <cpu/x86/msr.h> #include <cpu/amd/msr.h> #include <inttypes.h> #include <northbridge/amd/amdht/AsPsDefs.h> diff --git a/src/cpu/amd/microcode/microcode.c b/src/cpu/amd/microcode/microcode.c index 68b6953..8ee9006 100644 --- a/src/cpu/amd/microcode/microcode.c +++ b/src/cpu/amd/microcode/microcode.c @@ -126,7 +126,7 @@ UCODE_DEBUG("patch id to apply = 0x%08x\n", m->patch_id);
/* read the patch_id again */ - msr = rdmsr(0x8b); + msr = rdmsr(IA32_BIOS_SIGN_ID); new_patch_id = msr.lo;
UCODE_DEBUG("updated to patch id = 0x%08x %s\n", new_patch_id, diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c index 7ba21fe..4654086 100644 --- a/src/cpu/x86/lapic/boot_cpu.c +++ b/src/cpu/x86/lapic/boot_cpu.c @@ -13,13 +13,14 @@
#include <smp/node.h> #include <cpu/x86/msr.h> +#include <cpu/x86/lapic_def.h>
#if IS_ENABLED(CONFIG_SMP) int boot_cpu(void) { int bsp; msr_t msr; - msr = rdmsr(0x1b); + msr = rdmsr(LAPIC_BASE_MSR); bsp = !!(msr.lo & (1 << 8)); return bsp; } diff --git a/src/cpu/x86/smm/smmhandler.S b/src/cpu/x86/smm/smmhandler.S index 98d67d3..8f42acd 100644 --- a/src/cpu/x86/smm/smmhandler.S +++ b/src/cpu/x86/smm/smmhandler.S @@ -21,7 +21,7 @@ * to 64k if we can though. */
-#define LAPIC_BASE_MSR 0x1b +#include <cpu/x86/lapic_def.h>
/* * +--------------------------------+ 0xaffff diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 032ce4e..8a524dc 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -11,6 +11,7 @@ #define EFER_SCE (1 << 0)
/* Page attribute type MSR */ +#define TSC_MSR 0x10 #define IA32_PLATFORM_ID 0x17 #define IA32_FEATURE_CONTROL 0x3a #define FEATURE_CONTROL_LOCK_BIT (1 << 0) diff --git a/src/northbridge/amd/amdht/AsPsDefs.h b/src/northbridge/amd/amdht/AsPsDefs.h index 7e6a63d..30f4d75 100644 --- a/src/northbridge/amd/amdht/AsPsDefs.h +++ b/src/northbridge/amd/amdht/AsPsDefs.h @@ -18,9 +18,6 @@ #ifndef ASPSDEFS_H #define ASPSDEFS_H
-#define APIC_BAR 0x1b /* APIC_BAR register */ -#define APIC_BAR_BP 0x100 /* APIC_BAR BSP bit */ - /* P-state register offset */ #define PS_REG0 0 /* offset for P0 */ #define PS_REG1 1 /* offset for P1 */ @@ -237,7 +234,6 @@ #define DUAL_PLANE_NB_VID_OFF_MASK 0x3e0000/* for CPU rev <= C */ #define DUAL_PLANE_NB_VID_SHIFT 17/* for CPU rev <= C */
- #define NM_PS_REG (is_fam15h()?8:5) /* number of P-state MSR registers */
/* sFidVidInit.outFlags defines */ @@ -259,7 +255,6 @@ #define VID_1_100V 0x12 /* 1.100V */ #define VID_1_175V 0x1E /* 1.175V */
- /* Nb Fid Code */ #define NB_FID_800M 0x00 /* 800MHz */
@@ -268,13 +263,9 @@ #define NB_DID_1 1
/* GH Logical ID */ - #define GH_REV_A2 0x4 /* GH Rev A2 logical ID, Upper half */
- -#define TSC_MSR 0x10 #define TSC_FREQ_SEL_SHIFT 24 - #define TSC_FREQ_SEL_MASK (1 << TSC_FREQ_SEL_SHIFT)
#define WAIT_PSTATE_TIMEOUT 80000000 /* 0.1 s , unit : 1.25 ns */ diff --git a/src/northbridge/amd/amdht/h3finit.c b/src/northbridge/amd/amdht/h3finit.c index 1e2d1a0..8a85734 100644 --- a/src/northbridge/amd/amdht/h3finit.c +++ b/src/northbridge/amd/amdht/h3finit.c @@ -29,6 +29,7 @@
#include <device/pci.h> #include <console/console.h> +#include <cpu/x86/lapic_def.h> #include <cpu/amd/msr.h> #include <device/pci_def.h> #include <device/pci_ids.h> @@ -42,10 +43,6 @@ *---------------------------------------------------------------------------- */
-/* APIC defines from amdgesa.inc, which can't be included in to c code. */ -#define APIC_Base_BSP 8 -#define APIC_Base 0x1b - #define NVRAM_LIMIT_HT_SPEED_200 0x12 #define NVRAM_LIMIT_HT_SPEED_300 0x11 #define NVRAM_LIMIT_HT_SPEED_400 0x10 @@ -1831,9 +1828,9 @@ { uint64 qValue;
- AmdMSRRead(APIC_Base, &qValue); + AmdMSRRead(LAPIC_BASE_MSR, &qValue);
- return ((qValue.lo & ((u32)1 << APIC_Base_BSP)) != 0); + return ((qValue.lo & LAPIC_BASE_MSR_BOOTSTRAP_PROCESSOR) != 0); }
/*************************************************************************** diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c index b94c68c..b4d1241 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mct_d.c @@ -2364,10 +2364,10 @@ uint64_t start_timestamp; uint64_t current_timestamp;
- tsc_msr = rdmsr(0x00000010); + tsc_msr = rdmsr(TSC_MSR); start_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo; do { - tsc_msr = rdmsr(0x00000010); + tsc_msr = rdmsr(TSC_MSR); current_timestamp = (((uint64_t)tsc_msr.hi) << 32) | tsc_msr.lo; } while ((current_timestamp - start_timestamp) < cycle_count); } diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c index 1db1b54..42627e8 100644 --- a/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c +++ b/src/northbridge/amd/amdmct/mct_ddr3/mctsrc.c @@ -2427,7 +2427,7 @@
cycles <<= 3; /* x8 (number of 1.25ns ticks) */
- msr = 0x10; /* TSC */ + msr = TSC_MSR; /* TSC */ _RDMSR(msr, &lo, &hi); saved = lo; do {