[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Correct FSP log interface

[Ronak Kanabar (Code Review)]

Ronak Kanabar has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/39280 )

Change subject: soc/intel/tigerlake: Correct FSP log interface
......................................................................

Patch Set 19:

(2 comments)

https://review.coreboot.org/c/coreboot/+/39280/17//COMMIT_MSG 
Commit Message:

https://review.coreboot.org/c/coreboot/+/39280/17//COMMIT_MSG@13 
PS17, Line 13: add
> Add

Done

https://review.coreboot.org/c/coreboot/+/39280/17/src/soc/intel/tigerlake/ro... 
File src/soc/intel/tigerlake/romstage/fsp_params_jsl.c:

https://review.coreboot.org/c/coreboot/+/39280/17/src/soc/intel/tigerlake/ro... 
PS17, Line 73:  UART configuration
> maybe: Set debug interface

Done