Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/48340 )
Change subject: soc/intel/alderlake: Revise PCIE port config ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/chi... File src/soc/intel/alderlake/chip.h:
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/chi... PS1, Line 126: PcieRp make it lowercase ?
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/rom... File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/48340/1/src/soc/intel/alderlake/rom... PS1, Line 48: PcieRp[i].clksrc can u please help me to understand, how this variable will get its value ?