the following patch was just integrated into master: commit cf38facbd2255562cfbf2a2bc528794fafa5891a Author: Alexandru Gagniuc mr.nuke.me@gmail.com Date: Sat Apr 19 16:22:53 2014 -0500
hp/pavilion_m6_1035dx: Map PCIE PME sources to GPE 0x18
The PCIE PME pin from the APU is connected to GEVENT8, but the northbridge's ASL hardcodes this to GPE 0x18. Adjust the SCI map accordingly.
Change-Id: Ie395e62919f6e97ef9bcc45c736f9debf4e09ba0 Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com Reviewed-on: http://review.coreboot.org/5556 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel paulepanter@users.sourceforge.net Reviewed-by: Aaron Durbin adurbin@gmail.com
See http://review.coreboot.org/5556 for details.
-gerrit