[coreboot-gerrit] Change in coreboot[master]: soc/intel/skylake: Improve comment for DISB

[Nico Huber (Code Review)]

Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/36650 )

Change subject: soc/intel/skylake: Improve comment for DISB
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Patch Set 1:

(1 comment)

https://review.coreboot.org/c/coreboot/+/36650/1/src/soc/intel/skylake/pmc.c 
File src/soc/intel/skylake/pmc.c:

https://review.coreboot.org/c/coreboot/+/36650/1/src/soc/intel/skylake/pmc.c... 
PS1, Line 39: this bit must be CLEARED
> This function is called _after_ DRAM init and it _sets_ the bit. So it is […]

I've added printk()s before/after the write below:

disb_val after FSP-M: 0xe0040200
    disb_val after pmc_set_disb(): 0xe0840200

Pretty much what I would have expected: FSP-M ends with the bit cleared
as the datasheet suggests. So I believe, neither the documentation nor
FSP is wrong. Coreboot is. We should make sure, though, by checking the
FSP code that interprets this bit.