Bruce Griffith (Bruce.Griffith@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/3842
-gerrit
commit d908aeda774026768dbf9ae05c857586c6c4f3df Author: Bruce Griffith bruce.griffith@se-eng.com Date: Mon Jul 29 20:59:06 2013 -0600
AMD Hudson: Add wrapper functions to enable LPC Super I/O ports
The current method for AMD platforms is to add 0xCD6/0xCD7 calls I/O writes into the mainboard code. Wrapper code was added at some point to enable Port 80s using a function. This change does the same, providing a call to enable the Super I/O ports with a similar function [hudson_lpc_superio()].
Change-Id: I796c0b2321af07da1b15645ba6d541fea614112f Signed-off-by: Bruce Griffith bruce.griffith@se-eng.com Reviewed-by: Dave Frodin dave.frodin@se-eng.com --- src/southbridge/amd/agesa/hudson/early_setup.c | 46 ++++++++++++++---- src/southbridge/amd/agesa/hudson/hudson.c | 65 +++++++++++++------------- src/southbridge/amd/agesa/hudson/hudson.h | 55 ++++++++++++++++++++-- 3 files changed, 119 insertions(+), 47 deletions(-)
diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 96861c9..42eb5d4 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -29,20 +29,46 @@ #include <cbmem.h> #include "hudson.h"
-void hudson_lpc_port80(void) +static device_t hudson_lpc_enable(void) { - u8 byte; + #define PMxEC_LPC_GATING_REG 0xEC + #define PMxEC_LPC_ENABLE_VALUE (1 << 0) + #define LPC_BUS_NUMBER 0 + #define LPC_DEVICE_NUMBER 0x14 + #define LPC_FUNCTION_NUMBER 3 + device_t dev;
/* Enable LPC controller */ - outb(0xEC, 0xCD6); - byte = inb(0xCD7); - byte |= 1; - outb(0xEC, 0xCD6); - outb(byte, 0xCD7); - - /* Enable port 80 LPC decode in pci function 3 configuration space. */ - dev = PCI_DEV(0, 0x14, 3);//pci_locate_device(PCI_ID(0x1002, 0x439D), 0); + pm_iowrite( + PMxEC_LPC_GATING_REG, + pm_ioread(PMxEC_LPC_GATING_REG) | PMxEC_LPC_ENABLE_VALUE + ); + + /* Locate the LPC controller (0x1022, 0x780E) */ + dev = PCI_DEV(LPC_BUS_NUMBER, LPC_DEVICE_NUMBER, LPC_FUNCTION_NUMBER); + + return dev; +} + + +void hudson_lpc_superio(void) +{ + const device_t dev = hudson_lpc_enable(); + u8 byte; + + /* Enable Super I/O configuration in LPC configuration space. */ + byte = pci_read_config8(dev, 0x48); + byte |= 3 << 0; /* enable Super I/O port 2E/2F, 4E/4F */ + pci_write_config8(dev, 0x48, byte); +} + +void hudson_lpc_port80(void) +{ + const device_t dev = hudson_lpc_enable(); + u8 byte; + + /* Enable port 80 LPC decode in LPC configuration space. */ byte = pci_read_config8(dev, 0x4a); byte |= 1 << 5; /* enable port 80 */ pci_write_config8(dev, 0x4a, byte); diff --git a/src/southbridge/amd/agesa/hudson/hudson.c b/src/southbridge/amd/agesa/hudson/hudson.c index 2139911..04489f6 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.c +++ b/src/southbridge/amd/agesa/hudson/hudson.c @@ -53,6 +53,38 @@ void backup_top_of_ram(uint64_t ramtop) } }
+//inline static void pmio_write_index(u16 port_base, u8 reg, u8 value) +//{ +// outb(reg, port_base); +// outb(value, port_base + 1); +//} +// +//inline static u8 pmio_read_index(u16 port_base, u8 reg) +//{ +// outb(reg, port_base); +// return inb(port_base + 1); +//} +// +//void pm_iowrite(u8 reg, u8 value) +//{ +// pmio_write_index(PM_INDEX, reg, value); +//} +// +//u8 pm_ioread(u8 reg) +//{ +// return pmio_read_index(PM_INDEX, reg); +//} +// +//void pm2_iowrite(u8 reg, u8 value) +//{ +// pmio_write_index(PM2_INDEX, reg, value); +//} +// +//u8 pm2_ioread(u8 reg) +//{ +// return pmio_read_index(PM2_INDEX, reg); +//} +// void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val) { u32 reg_old, reg; @@ -64,39 +96,6 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val) } }
-static void pmio_write_index(u16 port_base, u8 reg, u8 value) -{ - outb(reg, port_base); - outb(value, port_base + 1); -} - -static u8 pmio_read_index(u16 port_base, u8 reg) -{ - outb(reg, port_base); - return inb(port_base + 1); -} - -void pm_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM_INDEX, reg, value); -} - -u8 pm_ioread(u8 reg) -{ - return pmio_read_index(PM_INDEX, reg); -} - -void pm2_iowrite(u8 reg, u8 value) -{ - pmio_write_index(PM2_INDEX, reg, value); -} - -u8 pm2_ioread(u8 reg) -{ - return pmio_read_index(PM2_INDEX, reg); -} - - void hudson_enable(device_t dev) { printk(BIOS_DEBUG, "hudson_enable()\n"); diff --git a/src/southbridge/amd/agesa/hudson/hudson.h b/src/southbridge/amd/agesa/hudson/hudson.h index e8f80aa..6e5ef23 100644 --- a/src/southbridge/amd/agesa/hudson/hudson.h +++ b/src/southbridge/amd/agesa/hudson/hudson.h @@ -20,6 +20,8 @@ #ifndef HUDSON_H #define HUDSON_H
+#include <config.h> +#include <arch/io.h> #include <device/pci_ids.h> #include <device/device.h> #include "chip.h" @@ -40,10 +42,10 @@ #define ACPI_GPE0_BLK (HUDSON_ACPI_IO_BASE + 0x10) /* 8 bytes */ #define ACPI_CPU_CONTROL (HUDSON_ACPI_IO_BASE + 0x08) /* 6 bytes */
-void pm_iowrite(u8 reg, u8 value); -u8 pm_ioread(u8 reg); -void pm2_iowrite(u8 reg, u8 value); -u8 pm2_ioread(u8 reg); +//void pm_iowrite(u8 reg, u8 value); +//u8 pm_ioread(u8 reg); +//void pm2_iowrite(u8 reg, u8 value); +//u8 pm2_ioread(u8 reg); void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val);
#define REV_HUDSON_A11 0x11 @@ -58,6 +60,7 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val); #define SPIROM_BASE_ADDRESS_REGISTER 0xA0
#ifdef __PRE_RAM__ +void hudson_lpc_superio(void); void hudson_lpc_port80(void); void hudson_pci_port80(void); void hudson_clk_output_48Mhz(void); @@ -74,4 +77,48 @@ void s3_resume_init_data(void *FchParams);
#endif
+#if IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_7) || IS_ENABLED(CONFIG_DEFAULT_CONSOLE_LOGLEVEL_8) +#define PMIO_OPTIMIZATION_PREFIX __attribute__((optimize("O0"))) +#define PMIO_STORAGE_PREFIX volatile +#else +#define PMIO_OPTIMIZATION_PREFIX +#define PMIO_STORAGE_PREFIX register +#endif + +static inline void PMIO_OPTIMIZATION_PREFIX pmio_write_index(u16 port_base, u8 reg, u8 value) +{ + outb(reg, port_base); + outb(value, port_base + 1); +} + +static inline u8 PMIO_OPTIMIZATION_PREFIX pmio_read_index(u16 port_base, u8 reg) +{ + PMIO_STORAGE_PREFIX u8 value; + outb(reg, port_base); + value = inb(port_base + 1); + return value; +} + +static inline void PMIO_OPTIMIZATION_PREFIX pm_iowrite(u8 reg, u8 value) +{ + pmio_write_index(PM_INDEX, reg, value); +} + +static inline u8 PMIO_OPTIMIZATION_PREFIX pm_ioread(u8 reg) +{ + PMIO_STORAGE_PREFIX const u8 value = pmio_read_index(PM_INDEX, reg); + return value; +} + +static inline void PMIO_OPTIMIZATION_PREFIX pm2_iowrite(u8 reg, u8 value) +{ + pmio_write_index(PM2_INDEX, reg, value); +} + +static inline u8 PMIO_OPTIMIZATION_PREFIX pm2_ioread(u8 reg) +{ + PMIO_STORAGE_PREFIX const u8 value = pmio_read_index(PM2_INDEX, reg); + return value; +} + #endif /* HUDSON_H */