[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Send End-of-Post message to CSE

[Tim Wawrzynczak (Code Review)]

Tim Wawrzynczak has submitted this change. ( https://review.coreboot.org/c/coreboot/+/55632 )

Change subject: soc/intel/tigerlake: Send End-of-Post message to CSE
......................................................................

soc/intel/tigerlake: Send End-of-Post message to CSE

This is done to ensure the CSE will not execute any pre-boot commands
after it receives this command. Verified EOP and error recovery sequence
from Intel doc#612229

Signed-off-by: Tim Wawrzynczak 
Change-Id: Iae6b2eac11c065749e57c5337d81ed20044fc903
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55632
Tested-by: build bot (Jenkins) 
Reviewed-by: Furquan Shaikh 
---
M src/soc/intel/tigerlake/Kconfig
M src/soc/intel/tigerlake/fsp_params.c
2 files changed, 7 insertions(+), 6 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Furquan Shaikh: Looks good to me, approved

diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig
index 7bc2ba2..e41d7a7 100644
--- a/src/soc/intel/tigerlake/Kconfig
+++ b/src/soc/intel/tigerlake/Kconfig
@@ -72,6 +72,7 @@
    select SOC_INTEL_COMMON_PCH_BASE
    select SOC_INTEL_COMMON_RESET
    select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT
+	select SOC_INTEL_CSE_SET_EOP
    select SSE2
    select SUPPORT_CPU_UCODE_IN_CBFS
    select TSC_MONOTONIC_TIMER
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 63332fe..e7fe51a 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -43,10 +43,10 @@
  * 2 - Send in DXE (Not applicable for FSP in API mode)
  */
 enum {
-	EOP_DISABLE,
-	EOP_PEI,
-	EOP_DXE,
-} EndOfPost;
+	EOP_DISABLE = 0,
+	EOP_PEI = 1,
+	EOP_DXE = 2,
+};

/*
  * Chip config parameter PcieRpL1Substates uses (UPD value + 1)
@@ -403,8 +403,8 @@
    	params->RtcMemoryLock = 1;
    }

-	/* Enable End of Post in PEI phase */
-	params->EndOfPostMessage = EOP_PEI;
+	/* coreboot will send EOP before loading payload */
+	params->EndOfPostMessage = EOP_DISABLE;

/* USB */
    for (i = 0; i < ARRAY_SIZE(config->usb2_ports); i++) {