Kyösti Mälkki has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/30800 )
Change subject: southbridge/intel/common/smbus: Add do_i2c_block_write() ......................................................................
Patch Set 20: Code-Review+1
(5 comments)
https://review.coreboot.org/#/c/30800/20//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/30800/20//COMMIT_MSG@13 PS20, Line 13: also write first byte to SMBHSTDAT1 End full sentences with period.
https://review.coreboot.org/#/c/30800/20//COMMIT_MSG@14 PS20, Line 14: he caller needs to configure the SMBus controller in i2c mode. The
https://review.coreboot.org/#/c/30800/20/src/southbridge/intel/common/smbus.... File src/southbridge/intel/common/smbus.c:
https://review.coreboot.org/#/c/30800/20/src/southbridge/intel/common/smbus.... PS20, Line 415: int do_i2c_block_write(unsigned int smbus_base, u8 device, Please add a comment the caller is currently (and sort of incorrectly) responsible of setting HOSTC I2C_EN bit prior to making this call.
https://review.coreboot.org/#/c/30800/20/src/southbridge/intel/common/smbus.... PS20, Line 436: * will generate the i2c sequence. Please file a bug thru the official channels to Intel on this.
https://review.coreboot.org/#/c/30800/20/src/southbridge/intel/common/smbus.... PS20, Line 441: outb(cmd, smbus_base + SMBHSTDAT1); I notice the order of CMD and DAT1 access changed. Hopefully the hardware is equally stable both ways.