[coreboot-gerrit] [S] Change in coreboot[master]: soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl

[Felix Held (Code Review)]

Attention is currently required from: Jason Glenesk, Jason Nien, Matt DeVillier, Martin Roth, Fred Reitberger.

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/69188 )

Change subject: soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl
......................................................................

soc/amd/picasso/acpi: include pci_int_defs.asl from soc.asl

Instead of including pci_int_defs.asl in each board's DSDT, include it
in the common soc.asl. This moves the PRQM OperationRegion and the PRQI
IndexField defined in pci_int_defs.asl into the _SB scope, but those
are defined inside the _SB scope both in the Picasso reference code and
for the AMD SoCs from Cezanne on.

TEST=Both Linux and Windows still boot and don't show ACPI errors on
Mandolin after moving this inside the _SB scope

Signed-off-by: Felix Held 
Change-Id: Ib4e7bfb15de184cc43cd17c8249be0f59405793f
---
M src/mainboard/amd/bilby/dsdt.asl
M src/mainboard/amd/mandolin/dsdt.asl
M src/mainboard/google/zork/dsdt.asl
M src/soc/amd/picasso/acpi/soc.asl
4 files changed, 22 insertions(+), 9 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/69188/1

diff --git a/src/mainboard/amd/bilby/dsdt.asl b/src/mainboard/amd/bilby/dsdt.asl
index 140f395..dd42608 100644
--- a/src/mainboard/amd/bilby/dsdt.asl
+++ b/src/mainboard/amd/bilby/dsdt.asl
@@ -16,9 +16,6 @@
    #include <acpi/dsdt_top.asl>
    #include <globalnvs.asl>

-	/* PCI IRQ mapping for the Southbridge */
-	#include <pci_int_defs.asl>
-
    /* Power state notification to ALIB */
    #include <pnot.asl>

diff --git a/src/mainboard/amd/mandolin/dsdt.asl b/src/mainboard/amd/mandolin/dsdt.asl
index 140f395..dd42608 100644
--- a/src/mainboard/amd/mandolin/dsdt.asl
+++ b/src/mainboard/amd/mandolin/dsdt.asl
@@ -16,9 +16,6 @@
    #include <acpi/dsdt_top.asl>
    #include <globalnvs.asl>

-	/* PCI IRQ mapping for the Southbridge */
-	#include <pci_int_defs.asl>
-
    /* Power state notification to ALIB */
    #include <pnot.asl>

diff --git a/src/mainboard/google/zork/dsdt.asl b/src/mainboard/google/zork/dsdt.asl
index 732ebea..62520b9 100644
--- a/src/mainboard/google/zork/dsdt.asl
+++ b/src/mainboard/google/zork/dsdt.asl
@@ -17,9 +17,6 @@
    #include <acpi/dsdt_top.asl>
    #include <globalnvs.asl>

-	/* PCI IRQ mapping for the Southbridge */
-	#include <pci_int_defs.asl>
-
    /* Power state notification to ALIB */
    #include <pnot.asl>

diff --git a/src/soc/amd/picasso/acpi/soc.asl b/src/soc/amd/picasso/acpi/soc.asl
index c4425eb..f44f873 100644
--- a/src/soc/amd/picasso/acpi/soc.asl
+++ b/src/soc/amd/picasso/acpi/soc.asl
@@ -8,6 +8,9 @@
    #include "sb_pci0_fch.asl"
 }

+/* PCI IRQ mapping for the Southbridge */
+#include "pci_int_defs.asl"
+
 /* Describe PCI INT[A-H] for the Southbridge */
 #include <soc/amd/common/acpi/pci_int.asl>