Marc Jones (marc.jones@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8009
-gerrit
commit 522ea9dea1c8d7890bdc2da0b787ad35b77e4e1d Author: Deepa Dinamani deepad@codeaurora.org Date: Tue May 13 13:49:42 2014 -0700
soc/ipq806x : Add CONFIG_TTB_BUFFER for the soc.
Define a base address for page table entries. Place it 64KB below the bootblock loading address.
BUG=chrome-os-partner:28467 TEST=verified that the page tables are being populated at this address. Also observed that the SPI driver takes 900 ns to process a byte as opposed to 1.5 us in case caching is not enabled.
Original-Change-Id: I3d8bd3104c55389aa5768033642ebbf1fda0fec7 Original-Signed-off-by: Deepa Dinamani deepad@codeaurora.org Original-Signed-off-by: Vadim Bendebury vbendeb@chromium.org Original-Reviewed-on: https://chromium-review.googlesource.com/200332 (cherry picked from commit 483dbea46c7d4c8ea8dbaf11bc82990f4cffff8c) Signed-off-by: Marc Jones marc.jones@se-eng.com
Change-Id: Ifef78b9bd6938533bed415ec99fd75a8031a7068 --- src/soc/qualcomm/ipq806x/Kconfig | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/src/soc/qualcomm/ipq806x/Kconfig b/src/soc/qualcomm/ipq806x/Kconfig index 4f081f0..3752c16 100644 --- a/src/soc/qualcomm/ipq806x/Kconfig +++ b/src/soc/qualcomm/ipq806x/Kconfig @@ -70,4 +70,8 @@ config CBFS_CACHE_SIZE hex "size of CBFS cache data" default 0x00016000
+config TTB_BUFFER + hex "memory address for page tables" + default 0x405f0000 + endif