Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/81338?usp=email )
Change subject: vc/amd/opensil/genoa_poc/mpio: add IFTYPE_ prefix to mpio_type values ......................................................................
vc/amd/opensil/genoa_poc/mpio: add IFTYPE_ prefix to mpio_type values
Add an IFTYPE_ prefix to all elements of the mpio_type enum to have more specific names.
Signed-off-by: Felix Held felix-coreboot@felixheld.de Change-Id: I229a3402c36941ee5347e3704fcf8d8a1bbc78a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/81338 Reviewed-by: Martin L Roth gaumless@gmail.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/amd/onyx_poc/devicetree.cb M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c M src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h 3 files changed, 16 insertions(+), 16 deletions(-)
Approvals: Martin L Roth: Looks good to me, approved build bot (Jenkins): Verified
diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb index 3597847..578bc42 100644 --- a/src/mainboard/amd/onyx_poc/devicetree.cb +++ b/src/mainboard/amd/onyx_poc/devicetree.cb @@ -57,7 +57,7 @@ device ref rcec_0 on end device ref gpp_bridge_0_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P2 - register "type" = "PCIE" + register "type" = "IFTYPE_PCIE" register "start_lane" = "48" register "end_lane" = "63" register "gpio_group" = "1" @@ -67,7 +67,7 @@ end device ref gpp_bridge_0_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G2 - register "type" = "PCIE" + register "type" = "IFTYPE_PCIE" register "start_lane" = "112" register "end_lane" = "127" register "gpio_group" = "1" @@ -78,7 +78,7 @@ end device ref gpp_bridge_0_0_c on chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "PCIE" + register "type" = "IFTYPE_PCIE" register "start_lane" = "128" register "end_lane" = "131" register "gpio_group" = "1" @@ -101,7 +101,7 @@ device ref rcec_1 on end device ref gpp_bridge_1_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P3 - register "type" = "PCIE" + register "type" = "IFTYPE_PCIE" register "start_lane" = "16" register "end_lane" = "31" register "gpio_group" = "1" @@ -111,7 +111,7 @@ end device ref gpp_bridge_1_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G3 - register "type" = "PCIE" + register "type" = "IFTYPE_PCIE" register "start_lane" = "80" register "end_lane" = "95" register "gpio_group" = "1" @@ -126,7 +126,7 @@ device ref rcec_2 on end device ref gpp_bridge_2_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P1 - register "type" = "PCIE" + register "type" = "IFTYPE_PCIE" register "start_lane" = "32" register "end_lane" = "47" register "gpio_group" = "1" @@ -137,7 +137,7 @@ end device ref gpp_bridge_2_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G1 - register "type" = "PCIE" + register "type" = "IFTYPE_PCIE" register "start_lane" = "64" register "end_lane" = "79" register "gpio_group" = "1" @@ -153,7 +153,7 @@ device ref rcec_3 on end device ref gpp_bridge_3_0_a on chip vendorcode/amd/opensil/genoa_poc/mpio # P0 - register "type" = "PCIE" + register "type" = "IFTYPE_PCIE" register "start_lane" = "0" register "end_lane" = "15" register "gpio_group" = "1" @@ -163,7 +163,7 @@ end device ref gpp_bridge_3_0_b on chip vendorcode/amd/opensil/genoa_poc/mpio # G0 - register "type" = "PCIE" + register "type" = "IFTYPE_PCIE" register "start_lane" = "96" register "end_lane" = "111" register "gpio_group" = "1" @@ -173,7 +173,7 @@ end device ref gpp_bridge_3_0_c on # WAFL chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "PCIE" + register "type" = "IFTYPE_PCIE" register "start_lane" = "132" register "end_lane" = "133" register "gpio_group" = "1" @@ -183,7 +183,7 @@ end device ref gpp_bridge_3_1_c on # BMC chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "PCIE" + register "type" = "IFTYPE_PCIE" register "start_lane" = "134" register "end_lane" = "134" register "gpio_group" = "1" @@ -194,7 +194,7 @@ end device ref gpp_bridge_3_2_c on # BMC chip vendorcode/amd/opensil/genoa_poc/mpio - register "type" = "PCIE" + register "type" = "IFTYPE_PCIE" register "start_lane" = "135" register "end_lane" = "135" register "gpio_group" = "1" diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c index 50e96c9..61233a9 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c @@ -141,7 +141,7 @@
static int mpio_port = 0; MPIO_PORT_DESCRIPTOR port = { .Flags = DESCRIPTOR_TERMINATE_LIST }; - if (config->type == PCIE) { + if (config->type == IFTYPE_PCIE) { const MPIO_ENGINE_DATA engine_data = MPIO_ENGINE_DATA_INITIALIZER(MpioPcieEngine, config->start_lane, config->end_lane, @@ -160,7 +160,7 @@ config->aspm_l1_2, config->clock_pm); port.Port = port_data; - } else if (config->type == SATA) { + } else if (config->type == IFTYPE_SATA) { const MPIO_ENGINE_DATA engine_data = MPIO_ENGINE_DATA_INITIALIZER(MpioSATAEngine, config->start_lane, config->end_lane, diff --git a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h index 64a8b3e..deb4038 100644 --- a/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h +++ b/src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h @@ -17,8 +17,8 @@ */
enum mpio_type { - PCIE, - SATA, + IFTYPE_PCIE, + IFTYPE_SATA, };
/* Sync with PCIE_HOTPLUG_TYPE */