Werner Zeh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/42879 )
Change subject: soc/intel/common/cpu: Don't set any TCC settings if offset is 0 ......................................................................
Patch Set 2:
(1 comment)
https://review.coreboot.org/c/coreboot/+/42879/2/src/soc/intel/common/block/... File src/soc/intel/common/block/cpu/cpulib.c:
https://review.coreboot.org/c/coreboot/+/42879/2/src/soc/intel/common/block/... PS2, Line 277: /* Time Window Tau Bits [6:0] */ : msr.lo &= ~0x7f; : msr.lo |= 0xe6; /* setting 100ms thermal time window */ : wrmsr(MSR_TEMPERATURE_TARGET, msr); If I have a look at the MSR documentation of Apollo Lake then I will find that bits 0..7 in MSR 0x1A2 are marked as reserved. With this code one could potentially still hit the error if for some reason tcc_offset is set in devicetree. I would rather see a platform differentiation choice here and execute this only on platforms that do support these bits (like Tiger Lake).
if (CONFIG(SOC_INTEL_TIGERLAKE) || CONFIG(WHAT_EVER_PLATFORM_SUPPORTS_THESE_BITS)) { msr = rdmsr(MSR_TEMPERATURE_TARGET); /* Time Window Tau Bits [6:0] */ msr.lo &= ~0x7f; msr.lo |= 0xe6; /* setting 100ms thermal time window */ wrmsr(MSR_TEMPERATURE_TARGET, msr); }