Attention is currently required from: Tim Wawrzynczak, Subrata Banik, Angel Pons, Patrick Rudolph, EricR Lai. Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/50162 )
Change subject: soc/intel/alderlake: Add support for external clock buffer ......................................................................
Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/50162/comment/17fdde1d_825d0a6e PS1, Line 9: 3 CLKSRC using external clock buffer. : CLKSRC 6 provides feed clock to discrete buffer for further : distribution to platform.
Could you share the schematic to me, just for the external clock part. […]
Thanks for the details, Angel! That makes sense to me.
Before we add any Kconfigs, I think we need to understand how the internal v/s external clock sources need to be described.
* Are these clocks associated with different root ports? --> My understanding is yes.
* How does FSP treat the internal v/s external clock sources?
What we know so far: * One of the internal clock sources needs to be configured as free running because it is used as input to external clock chip. * The external clock chip generates upto 4 external clock sources. * These external clock sources can be requested by CLKREQ# signals 7-10 which result in PCH driving the OE# signals going to the external clock chip.
Subrata - do you have any documentation that talks more about how the external clock chip configuration really works i.e. usage of OE# pins and CLKSRC/CLKREQ configuration, etc.