[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Move GPIO PM configuration to soc level

[Subrata Banik (Code Review)]

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37685 )

Change subject: soc/intel/cannonlake: Move GPIO PM configuration to soc level
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Patch Set 7:

(1 comment)

https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... 
File src/soc/intel/cannonlake/acpi/lpit.asl:

https://review.coreboot.org/c/coreboot/+/37685/5/src/soc/intel/cannonlake/ac... 
PS5, Line 79: /* Enable GPIO PM */
            : 				_SB.PCI0.LOCL (MISCCFG_ENABLE_GPIO_PM_CONFIG)
> If we think setting MISCCFG_ENABLE_GPIO_PM_CONFIG on the way into S0ix on all systems is OK then cou […]

if we only need to decide between 0 or 0x3f then we can avoid NVS and do the required changes in _PTS and _WAK but if we bother about other bit options as devicetree.cb might not only have 0 or 0x3f rather user might device to enable selective bits between 0-5 then S0ix implementation won't honor that part. I guess this was the reason why Furquan said NVS might take those data from .cb to .asl ?