[coreboot-gerrit] Change in coreboot[master]: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M

[Andrey Petrov (Code Review)]

Andrey Petrov has submitted this change. ( https://review.coreboot.org/c/coreboot/+/40735 )

Change subject: mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M
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mb/cedarisland_crb: exclude GPIOs reconfiguration by FSP-M

We should be sure that after romstage the pads will be configured
according to the config from gpio.h only. This patch sets the GPIO
configuration from gpio.h using the soc/intel/common/gpio.c driver
again in ramstage.

[1] https://review.coreboot.org/c/coreboot/+/40730

Change-Id: Ic49e504d96fe4fd44434e7b981f8d8d9e76880ef
Signed-off-by: Maxim Polyakov 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40735
Tested-by: build bot (Jenkins) 
Reviewed-by: Andrey Petrov 
---
A src/mainboard/intel/cedarisland_crb/ramstage.c
1 file changed, 11 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Andrey Petrov: Looks good to me, approved

diff --git a/src/mainboard/intel/cedarisland_crb/ramstage.c b/src/mainboard/intel/cedarisland_crb/ramstage.c
new file mode 100644
index 0000000..f4c716e
--- /dev/null
+++ b/src/mainboard/intel/cedarisland_crb/ramstage.c
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#include <soc/ramstage.h>
+#include "include/gpio.h"
+
+void mainboard_silicon_init_params(FSPS_UPD *params)
+{
+	/* configure Lewisburg PCH GPIO controller after FSP-M */
+	gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
+}