[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En

[John Zhao (Code Review)]

Hello Furquan Shaikh, Wonkyu Kim, Duncan Laurie, Patrick Rudolph,

I'd like you to reexamine a change. Please visit

https://review.coreboot.org/c/coreboot/+/41812

to look at the new patch set (#2).

Change subject: soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En
......................................................................

soc/intel/tigerlake: Configure TcssDma0En and TcssDma1En

Determine the TcssDma0 and TcssDma1 enabling based on TBT DMA
controllers setting.

BUG=:b:146624360
TEST=Booted on Volteer and verified TcssDma0 and TcssDma1 enabling.
lspci shows TcssDma0(0d.2) and TcssDma1(0d.3).

Signed-off-by: John Zhao 
Change-Id: I61ac4131481374e9a2a34d1a30f822046c3897fb
---
M src/soc/intel/tigerlake/chip.h
M src/soc/intel/tigerlake/romstage/fsp_params.c
2 files changed, 11 insertions(+), 6 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/12/41812/2