Kyösti Mälkki (kyosti.malkki@gmail.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/7096
-gerrit
commit 7e078b41e404f143b98c518756b2b5f16fae2e72 Author: Kyösti Mälkki kyosti.malkki@gmail.com Date: Thu Oct 16 12:47:25 2014 +0300
x86 romstage: Move stack just below RAMTOP
Placement of romstage stack in RAM was vulnerable for getting corrupted by decompressed ramstage.
Change-Id: Ic032bd3e69f4ab8dab8e5932df39fab70aa3e769 Signed-off-by: Kyösti Mälkki kyosti.malkki@gmail.com --- src/arch/x86/init/crt0_romcc_epilogue.inc | 2 +- src/arch/x86/init/prologue.inc | 1 - src/cpu/intel/car/cache_as_ram.inc | 3 +- src/cpu/intel/car/cache_as_ram_ht.inc | 3 +- src/cpu/intel/haswell/cache_as_ram.inc | 1 - src/cpu/intel/haswell/romstage.c | 3 +- src/cpu/intel/model_2065x/cache_as_ram.inc | 3 +- src/cpu/intel/model_206ax/cache_as_ram.inc | 3 +- src/cpu/intel/model_6ex/cache_as_ram.inc | 3 +- src/cpu/via/car/cache_as_ram.inc | 3 +- src/drivers/intel/fsp/cache_as_ram.inc | 1 - src/drivers/intel/fsp/fsp_util.c | 3 +- src/include/cpu/x86/stack.h | 32 ---------------------- .../emulation/qemu-i440fx/cache_as_ram.inc | 3 +- .../intel/fsp_rangeley/fsp/chipset_fsp_util.c | 1 - .../intel/fsp_sandybridge/fsp/chipset_fsp_util.c | 1 - src/soc/intel/baytrail/romstage/cache_as_ram.inc | 1 - src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c | 1 - 18 files changed, 10 insertions(+), 58 deletions(-)
diff --git a/src/arch/x86/init/crt0_romcc_epilogue.inc b/src/arch/x86/init/crt0_romcc_epilogue.inc index 419418d..791ab8e 100644 --- a/src/arch/x86/init/crt0_romcc_epilogue.inc +++ b/src/arch/x86/init/crt0_romcc_epilogue.inc @@ -11,7 +11,7 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* clear direction flag */
- movl $ROMSTAGE_STACK, %esp + movl $CONFIG_RAMTOP, %esp movl %esp, %ebp call copy_and_run
diff --git a/src/arch/x86/init/prologue.inc b/src/arch/x86/init/prologue.inc index 84e465c..bef42a3 100644 --- a/src/arch/x86/init/prologue.inc +++ b/src/arch/x86/init/prologue.inc @@ -18,7 +18,6 @@ */
#include <cpu/x86/post_code.h> -#include <cpu/x86/stack.h>
.section ".rom.data", "a", @progbits .section ".rom.text", "ax", @progbits diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc index 1ea50b8..843ca2d 100644 --- a/src/cpu/intel/car/cache_as_ram.inc +++ b/src/cpu/intel/car/cache_as_ram.inc @@ -21,7 +21,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/lapic_def.h> @@ -361,7 +360,7 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */
- movl $ROMSTAGE_STACK, %esp + movl $CONFIG_RAMTOP, %esp movl %esp, %ebp call copy_and_run
diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc index fb65316..265cd4f 100644 --- a/src/cpu/intel/car/cache_as_ram_ht.inc +++ b/src/cpu/intel/car/cache_as_ram_ht.inc @@ -20,7 +20,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -430,7 +429,7 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */
- movl $ROMSTAGE_STACK, %esp + movl $CONFIG_RAMTOP, %esp movl %esp, %ebp call copy_and_run
diff --git a/src/cpu/intel/haswell/cache_as_ram.inc b/src/cpu/intel/haswell/cache_as_ram.inc index 36d5654..51ac536 100644 --- a/src/cpu/intel/haswell/cache_as_ram.inc +++ b/src/cpu/intel/haswell/cache_as_ram.inc @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index 9e27668..65ee3b4 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -25,7 +25,6 @@ #include <cpu/x86/bist.h> #include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> -#include <cpu/x86/stack.h> #include <lib.h> #include <timestamp.h> #include <arch/io.h> @@ -85,7 +84,7 @@ static unsigned long choose_top_of_stack(void) ROMSTAGE_RAM_STACK_SIZE); stack_top += ROMSTAGE_RAM_STACK_SIZE; #else - stack_top = ROMSTAGE_STACK; + stack_top = CONFIG_RAMTOP; #endif return stack_top; } diff --git a/src/cpu/intel/model_2065x/cache_as_ram.inc b/src/cpu/intel/model_2065x/cache_as_ram.inc index 21f626b..43d51da 100644 --- a/src/cpu/intel/model_2065x/cache_as_ram.inc +++ b/src/cpu/intel/model_2065x/cache_as_ram.inc @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -278,7 +277,7 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */
- movl $ROMSTAGE_STACK, %esp + movl $CONFIG_RAMTOP, %esp movl %esp, %ebp call copy_and_run
diff --git a/src/cpu/intel/model_206ax/cache_as_ram.inc b/src/cpu/intel/model_206ax/cache_as_ram.inc index 1a19707..bf377f5 100644 --- a/src/cpu/intel/model_206ax/cache_as_ram.inc +++ b/src/cpu/intel/model_206ax/cache_as_ram.inc @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -311,7 +310,7 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */
- movl $ROMSTAGE_STACK, %esp + movl $CONFIG_RAMTOP, %esp movl %esp, %ebp call copy_and_run
diff --git a/src/cpu/intel/model_6ex/cache_as_ram.inc b/src/cpu/intel/model_6ex/cache_as_ram.inc index baf4ae8..09b8e93 100644 --- a/src/cpu/intel/model_6ex/cache_as_ram.inc +++ b/src/cpu/intel/model_6ex/cache_as_ram.inc @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -224,7 +223,7 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */
- movl $ROMSTAGE_STACK, %esp + movl $CONFIG_RAMTOP, %esp movl %esp, %ebp call copy_and_run
diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc index 17b4b83..c8a7e40 100644 --- a/src/cpu/via/car/cache_as_ram.inc +++ b/src/cpu/via/car/cache_as_ram.inc @@ -25,7 +25,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <console/post_codes.h> @@ -268,7 +267,7 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */
- movl $ROMSTAGE_STACK, %esp + movl $CONFIG_RAMTOP, %esp movl %esp, %ebp call copy_and_run
diff --git a/src/drivers/intel/fsp/cache_as_ram.inc b/src/drivers/intel/fsp/cache_as_ram.inc index 40787b5..0fc33cb 100644 --- a/src/drivers/intel/fsp/cache_as_ram.inc +++ b/src/drivers/intel/fsp/cache_as_ram.inc @@ -19,7 +19,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> diff --git a/src/drivers/intel/fsp/fsp_util.c b/src/drivers/intel/fsp/fsp_util.c index a9b5624..e15c82e 100644 --- a/src/drivers/intel/fsp/fsp_util.c +++ b/src/drivers/intel/fsp/fsp_util.c @@ -19,7 +19,6 @@
#include <types.h> #include <string.h> -#include <cpu/x86/stack.h> #include <console/console.h> #include <bootstate.h> #include <cbmem.h> @@ -81,7 +80,7 @@ void __attribute__ ((noreturn)) fsp_early_init (FSP_INFO_HEADER *fsp_ptr) #endif
memset((void*)&FspRtBuffer, 0, sizeof(FSP_INIT_RT_BUFFER)); - FspRtBuffer.Common.StackTop = (u32 *)ROMSTAGE_STACK; + FspRtBuffer.Common.StackTop = (u32 *)CONFIG_RAMTOP; FspInitParams.NvsBufferPtr = NULL;
#if IS_ENABLED(CONFIG_FSP_USES_UPD) diff --git a/src/include/cpu/x86/stack.h b/src/include/cpu/x86/stack.h deleted file mode 100644 index 158b670..0000000 --- a/src/include/cpu/x86/stack.h +++ /dev/null @@ -1,32 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2010 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA - */ - -#ifndef __CPU_X86_STACK_H -#define __CPU_X86_STACK_H - -/* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This - * makes sure that we stay completely within the 1M-64K of memory that we - * preserve for suspend/resume. This is basically HIGH_MEMORY_SAFE (see - * cbmem.h) - */ - -#define ROMSTAGE_STACK_OFFSET ( (1024 - 64) * 1024 ) -#define ROMSTAGE_STACK (CONFIG_RAMBASE + ROMSTAGE_STACK_OFFSET) - -#endif diff --git a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc index 9e47473..ce54c51 100644 --- a/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc +++ b/src/mainboard/emulation/qemu-i440fx/cache_as_ram.inc @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> @@ -63,7 +62,7 @@ __main: post_code(POST_PREPARE_RAMSTAGE) cld /* Clear direction flag. */
- movl $ROMSTAGE_STACK, %esp + movl $CONFIG_RAMTOP, %esp movl %esp, %ebp call copy_and_run
diff --git a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c index bd196a5..ae95087 100644 --- a/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_rangeley/fsp/chipset_fsp_util.c @@ -19,7 +19,6 @@
#include <types.h> #include <string.h> -#include <cpu/x86/stack.h> #include <console/console.h> #include <bootstate.h> #include <cbmem.h> diff --git a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c index 0537c54..a666d70 100644 --- a/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c +++ b/src/northbridge/intel/fsp_sandybridge/fsp/chipset_fsp_util.c @@ -19,7 +19,6 @@
#include <types.h> #include <string.h> -#include <cpu/x86/stack.h> #include <console/console.h> #include <bootstate.h> #include <cbmem.h> diff --git a/src/soc/intel/baytrail/romstage/cache_as_ram.inc b/src/soc/intel/baytrail/romstage/cache_as_ram.inc index f6e029d..b6fcbf2 100644 --- a/src/soc/intel/baytrail/romstage/cache_as_ram.inc +++ b/src/soc/intel/baytrail/romstage/cache_as_ram.inc @@ -18,7 +18,6 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */
-#include <cpu/x86/stack.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/cache.h> #include <cpu/x86/post_code.h> diff --git a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c index 83a1100..82f83a9 100644 --- a/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c +++ b/src/soc/intel/fsp_baytrail/fsp/chipset_fsp_util.c @@ -19,7 +19,6 @@
#include <types.h> #include <string.h> -#include <cpu/x86/stack.h> #include <console/console.h> #include <bootstate.h> #include <cbmem.h>