Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/34541 )
Change subject: soc/intel/cannonlake: Allow coreboot to handle required chipset lockdown ......................................................................
Patch Set 2:
(4 comments)
https://review.coreboot.org/c/coreboot/+/34541/2//COMMIT_MSG Commit Message:
https://review.coreboot.org/c/coreboot/+/34541/2//COMMIT_MSG@9 PS2, Line 9: let
lets
Done
https://review.coreboot.org/c/coreboot/+/34541/2//COMMIT_MSG@10 PS2, Line 10: chipset lockdown in ramstage.
Why does coreboot need the chipset to be unlocked in ramstage?
its like coreboot don't want FSP to lock down chipset during FSP-S and we (CB) might still using SPI registers to store "some" data hence we prefers FSP skip locking and cb locked those registers in finalize.c at end of POST
https://review.coreboot.org/c/coreboot/+/34541/2//COMMIT_MSG@13 PS2, Line 13: suggested
suggests
Done
https://review.coreboot.org/c/coreboot/+/34541/2/src/soc/intel/cannonlake/fs... File src/soc/intel/cannonlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/34541/2/src/soc/intel/cannonlake/fs... PS2, Line 420: Spi
SPI
Done