Attention is currently required from: Tarun Tuli, Kapil Porwal.
Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/74805 )
Change subject: soc/intel: Make CSE sync in romstage default disable ......................................................................
soc/intel: Make CSE sync in romstage default disable
This patch makes CSE sync in romstage default disabled to allow respective SoC platforms to choose the applicable CSE sync option between romstage (early) or ramstage (late).
Moved the CSE sync selection into the SoC directory based on the CSE sku type is CSE Lite.
Additionally, fix the alphabetic order before adding CSE sync related config inside the SoC directory.
TEST=Able to build google/marasov with this change where CSE sync is performed early inside romstage.
Signed-off-by: Subrata Banik subratabanik@google.com Change-Id: I3f5017fbcf917201eaf8233089050bd31c3d1917 --- M src/soc/intel/alderlake/Kconfig M src/soc/intel/cannonlake/Kconfig M src/soc/intel/common/block/cse/Kconfig M src/soc/intel/jasperlake/Kconfig M src/soc/intel/meteorlake/Kconfig M src/soc/intel/tigerlake/Kconfig 6 files changed, 36 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/05/74805/1
diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index cce2052..7d33aa7 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -7,6 +7,7 @@
config SOC_INTEL_RAPTORLAKE bool + select SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE if SOC_INTEL_CSE_LITE_SKU select X86_INIT_NEED_1_SIPI help Intel Raptorlake support. Mainboards using RPL should select @@ -15,21 +16,24 @@ config SOC_INTEL_ALDERLAKE_PCH_M bool select SOC_INTEL_ALDERLAKE + select SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE if SOC_INTEL_CSE_LITE_SKU help Choose this option if your mainboard has a PCH-M chipset.
config SOC_INTEL_ALDERLAKE_PCH_N bool - select SOC_INTEL_ALDERLAKE select MICROCODE_BLOB_UNDISCLOSED + select SOC_INTEL_ALDERLAKE + select SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE if SOC_INTEL_CSE_LITE_SKU help Choose this option if your mainboard has a PCH-N chipset.
config SOC_INTEL_ALDERLAKE_PCH_P bool - select SOC_INTEL_ALDERLAKE select HAVE_INTEL_FSP_REPO select PLATFORM_USES_FSP2_3 + select SOC_INTEL_ALDERLAKE + select SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE if SOC_INTEL_CSE_LITE_SKU help Choose this option if your mainboard has a PCH-P chipset.
diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index 33025eb..ae3f0fa 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -112,6 +112,7 @@ select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET + select SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE if SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION select SSE2 select SUPPORT_CPU_UCODE_IN_CBFS diff --git a/src/soc/intel/common/block/cse/Kconfig b/src/soc/intel/common/block/cse/Kconfig index 4a86882..dac1081 100644 --- a/src/soc/intel/common/block/cse/Kconfig +++ b/src/soc/intel/common/block/cse/Kconfig @@ -248,7 +248,7 @@
config SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE bool - default y + default n depends on SOC_INTEL_CSE_LITE_SKU && !SOC_INTEL_CSE_LITE_COMPRESS_ME_RW help Use default flow of CSE FW Update in romstage when uncompressed ME_RW blobs are used. diff --git a/src/soc/intel/jasperlake/Kconfig b/src/soc/intel/jasperlake/Kconfig index 660b24a..ee502e0 100644 --- a/src/soc/intel/jasperlake/Kconfig +++ b/src/soc/intel/jasperlake/Kconfig @@ -37,6 +37,7 @@ select PMC_GLOBAL_RESET_ENABLE_LOCK select SOC_INTEL_COMMON select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE + select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_COMMON_BLOCK select SOC_INTEL_COMMON_BLOCK_ACPI select SOC_INTEL_COMMON_BLOCK_ACPI_CPPC @@ -62,6 +63,7 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET + select SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE if SOC_INTEL_CSE_LITE_SKUT select SOC_INTEL_CSE_SEND_EOP_LATE select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION @@ -73,7 +75,6 @@ select USE_FSP_NOTIFY_PHASE_POST_PCI_ENUM select USE_FSP_NOTIFY_PHASE_READY_TO_BOOT select USE_FSP_NOTIFY_PHASE_END_OF_FIRMWARE - select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
config DCACHE_RAM_BASE default 0xfef00000 diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 7762d5f..ea88dfb 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -70,6 +70,7 @@ select SOC_INTEL_COMMON_BLOCK_HDA select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC select SOC_INTEL_COMMON_BLOCK_IPU + select SOC_INTEL_COMMON_BLOCK_IOC select SOC_INTEL_COMMON_BLOCK_IOE_P2SB select SOC_INTEL_COMMON_BLOCK_IRQ select SOC_INTEL_COMMON_BLOCK_ME_SPEC_18 @@ -88,7 +89,7 @@ select SOC_INTEL_COMMON_FSP_RESET select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET - select SOC_INTEL_COMMON_BLOCK_IOC + select SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE if SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index 9bca895..fd355429 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -82,6 +82,7 @@ select SOC_INTEL_COMMON_PCH_CLIENT select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_BLOCK_POWER_LIMIT + select SOC_INTEL_CSE_LITE_SYNC_IN_ROMSTAGE if SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_SEND_EOP_LATE select SOC_INTEL_CSE_SET_EOP select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION