Attention is currently required from: Nico Huber, Tim Wawrzynczak, Subrata Banik, Angel Pons, Michael Niewöhner, EricR Lai. Hello build bot (Jenkins), Furquan Shaikh, Patrick Georgi, Martin Roth, Tim Wawrzynczak, Subrata Banik, Angel Pons, Meera Ravindranath, Patrick Rudolph,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/48340
to look at the new patch set (#63).
Change subject: soc/intel/alderlake: Refactor PCIE port config ......................................................................
soc/intel/alderlake: Refactor PCIE port config
Refactor PCIE port config structure. Make it easier to map from schematic. We don't have to convert the PCIE ports RP number and CLK source in devicetree. All the convert will be done by SoC level.
Signed-off-by: Eric Lai ericr_lai@compal.corp-partner.google.com Change-Id: I0b390e43f8e99b19cfad178139b86a2f77d7a57b --- M src/mainboard/google/brya/variants/baseboard/devicetree.cb M src/mainboard/intel/adlrvp/devicetree.cb M src/soc/intel/alderlake/bootblock/pch.c M src/soc/intel/alderlake/bootblock/report_platform.c M src/soc/intel/alderlake/chip.h M src/soc/intel/alderlake/fsp_params.c D src/soc/intel/alderlake/include/soc/pch.h M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/uart.c M src/soc/intel/common/block/include/intelblocks/pcie_rp.h 10 files changed, 210 insertions(+), 161 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/48340/63