Marc Jones (marc.jones@se-eng.com) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/8644
-gerrit
commit 653a530d6a270519ee0c25fb9a765fadbf7fcbac Author: Tom Warren twarren@nvidia.com Date: Tue Jul 15 10:34:19 2014 -0700
tegra132: Add code to setup chip operations and mem resources.
With this memory resource, the payload loading code should be able to create a bounce buffer and load the payload successfully.
Adapted from tegra124 soc.c
BUG=None BRANCH=None TEST=Built and booted to ramstage on rush.
Original-Change-Id: I2e336ce93c1b0236104e63d3785f0e3d7d76bb01 Original-Signed-off-by: Tom Warren twarren@nvidia.com Original-Reviewed-on: https://chromium-review.googlesource.com/208121 Original-Reviewed-by: Aaron Durbin adurbin@chromium.org (cherry picked from commit 20765da0b15ee8c35a5bbfe532331fc6b1cef502) Signed-off-by: Marc Jones marc.jones@se-eng.com
Change-Id: I267ced473ad0773b52f889dfa83c65562444c01f --- src/soc/nvidia/tegra132/Makefile.inc | 1 + src/soc/nvidia/tegra132/soc.c | 81 ++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+)
diff --git a/src/soc/nvidia/tegra132/Makefile.inc b/src/soc/nvidia/tegra132/Makefile.inc index 0ab95d4..f8d4a4c 100644 --- a/src/soc/nvidia/tegra132/Makefile.inc +++ b/src/soc/nvidia/tegra132/Makefile.inc @@ -41,6 +41,7 @@ ramstage-y += cbfs.c ramstage-y += cbmem.c ramstage-y += timer.c ramstage-y += clock.c +ramstage-y += soc.c ramstage-y += spi.c ramstage-y += i2c.c ramstage-y += dma.c diff --git a/src/soc/nvidia/tegra132/soc.c b/src/soc/nvidia/tegra132/soc.c new file mode 100644 index 0000000..3a419bc --- /dev/null +++ b/src/soc/nvidia/tegra132/soc.c @@ -0,0 +1,81 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + * Copyright 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <device/device.h> +#include <arch/io.h> +#include <vendorcode/google/chromeos/chromeos.h> +#include <soc/addressmap.h> + +static void soc_read_resources(device_t dev) +{ + unsigned long index = 0; + int i; uintptr_t begin, end; + size_t size; + + printk(BIOS_DEBUG, "%s: entry, device = %p\n", __func__, dev); + for (i = 0; i < CARVEOUT_NUM; i++) { + carveout_range(i, &begin, &size); + if (size == 0) + continue; + reserved_ram_resource(dev, index++, begin * KiB, size * KiB); + } + + /* + * TODO: Frame buffer needs to handled as a carveout from the below_4G + * uintptr_t framebuffer_begin = framebuffer_attributes(&framebuffer_size); + */ + + + memory_in_range_below_4gb(&begin, &end); + size = end - begin; + ram_resource(dev, index++, begin * KiB, size * KiB); + + memory_in_range_above_4gb(&begin, &end); + size = end - begin; + ram_resource(dev, index++, begin * KiB, size * KiB); +} + +static void soc_init(device_t dev) +{ + printk(BIOS_INFO, "CPU: Tegra132\n"); +} + +static void soc_noop(device_t dev) +{ +} + +static struct device_operations soc_ops = { + .read_resources = soc_read_resources, + .set_resources = soc_noop, + .enable_resources = soc_noop, + .init = soc_init, + .scan_bus = 0, +}; + +static void enable_tegra132_dev(device_t dev) +{ + dev->ops = &soc_ops; +} + +struct chip_operations soc_nvidia_tegra132_ops = { + CHIP_NAME("SOC Nvidia Tegra132") + .enable_dev = enable_tegra132_dev, +};