[coreboot-gerrit] Change in coreboot[master]: soc/intel: Add Intel Xeon Scalable Processor support

[Aaron Durbin (Code Review)]

Aaron Durbin has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/38548 )

Change subject: soc/intel: Add Intel Xeon Scalable Processor support
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Patch Set 44:

(1 comment)

https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... 
File src/soc/intel/xeon_sp/bootblock/bootblock.c:

https://review.coreboot.org/c/coreboot/+/38548/41/src/soc/intel/xeon_sp/boot... 
PS41, Line 33: 		.CodeRegionBase = (UINT32)(0x100000000ULL - CONFIG_CBFS_SIZE),
             : 		.CodeRegionLength = (UINT32)CONFIG_CBFS_SIZE,
> No disconnect on your recommendation!! There is regression with this change - hangs post silicon ini […]

So this change is causing a regression? Why land something that is broken? There's also only so much mmio space for memory mapped spi flash. The spi flash size can definitely exceed the available mmio space. I agree with Andrey that CB:39050 is the correct way to achieve the desired results. Perhaps providing more details on the 'regression' would help in evaluating correct path forward.