Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/48658 )
Change subject: soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges() ......................................................................
soc/intel/*: Add TPM decode range to soc_get_fixed_mmio_ranges()
The TPM memory MMIO range is always decoded by the PCH, regardless if it's LPC, SPI or fTPM.
Add the memory range to fixed MMIO ranges list to prevent LGMR register being written with this address. Reserved 8 KiB as that seems to be the minimal common reserved size for the TPM MMIO area.
Change-Id: I8f2257b55a712b936763cfd289c2c4b1633e8049 Signed-off-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/soc/intel/alderlake/espi.c M src/soc/intel/apollolake/lpc.c M src/soc/intel/cannonlake/lpc.c M src/soc/intel/elkhartlake/espi.c M src/soc/intel/icelake/espi.c M src/soc/intel/jasperlake/espi.c M src/soc/intel/skylake/lpc.c M src/soc/intel/tigerlake/espi.c M src/soc/intel/xeon_sp/lpc.c 9 files changed, 18 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/48658/1
diff --git a/src/soc/intel/alderlake/espi.c b/src/soc/intel/alderlake/espi.c index c909030..f3c445a 100644 --- a/src/soc/intel/alderlake/espi.c +++ b/src/soc/intel/alderlake/espi.c @@ -27,6 +27,8 @@ */ static const struct lpc_mmio_range lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
diff --git a/src/soc/intel/apollolake/lpc.c b/src/soc/intel/apollolake/lpc.c index ad9211b9..91b4b6e 100644 --- a/src/soc/intel/apollolake/lpc.c +++ b/src/soc/intel/apollolake/lpc.c @@ -9,7 +9,8 @@ #include "chip.h"
static const struct lpc_mmio_range apl_lpc_fixed_mmio_ranges[] = { - { 0xfed40000, 0x8000 }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0xfedc0000, 0x4000 }, { 0xfed20800, 16 }, { 0xfed20880, 8 }, diff --git a/src/soc/intel/cannonlake/lpc.c b/src/soc/intel/cannonlake/lpc.c index b21c117..b72c298 100644 --- a/src/soc/intel/cannonlake/lpc.c +++ b/src/soc/intel/cannonlake/lpc.c @@ -25,6 +25,8 @@ */ static const struct lpc_mmio_range cnl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
diff --git a/src/soc/intel/elkhartlake/espi.c b/src/soc/intel/elkhartlake/espi.c index a531fcc..1ecd929 100644 --- a/src/soc/intel/elkhartlake/espi.c +++ b/src/soc/intel/elkhartlake/espi.c @@ -23,6 +23,8 @@ */ static const struct lpc_mmio_range ehl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
diff --git a/src/soc/intel/icelake/espi.c b/src/soc/intel/icelake/espi.c index 7f9ff2f..e4977be 100644 --- a/src/soc/intel/icelake/espi.c +++ b/src/soc/intel/icelake/espi.c @@ -24,6 +24,8 @@ */ static const struct lpc_mmio_range icl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
diff --git a/src/soc/intel/jasperlake/espi.c b/src/soc/intel/jasperlake/espi.c index 0977857..3370999 100644 --- a/src/soc/intel/jasperlake/espi.c +++ b/src/soc/intel/jasperlake/espi.c @@ -24,6 +24,8 @@ */ static const struct lpc_mmio_range jsl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
diff --git a/src/soc/intel/skylake/lpc.c b/src/soc/intel/skylake/lpc.c index f9c6639..7c80cbf 100644 --- a/src/soc/intel/skylake/lpc.c +++ b/src/soc/intel/skylake/lpc.c @@ -21,6 +21,8 @@
static const struct lpc_mmio_range skl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
diff --git a/src/soc/intel/tigerlake/espi.c b/src/soc/intel/tigerlake/espi.c index acd3b12..d4ea81a 100644 --- a/src/soc/intel/tigerlake/espi.c +++ b/src/soc/intel/tigerlake/espi.c @@ -30,6 +30,8 @@ */ static const struct lpc_mmio_range tgl_lpc_fixed_mmio_ranges[] = { { PCH_PRESERVED_BASE_ADDRESS, PCH_PRESERVED_BASE_SIZE }, + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };
diff --git a/src/soc/intel/xeon_sp/lpc.c b/src/soc/intel/xeon_sp/lpc.c index 3169545..370a020 100644 --- a/src/soc/intel/xeon_sp/lpc.c +++ b/src/soc/intel/xeon_sp/lpc.c @@ -10,6 +10,8 @@ #include <chip.h>
static const struct lpc_mmio_range xeon_lpc_fixed_mmio_ranges[] = { + { CONFIG_CRB_TPM_BASE_ADDRESS, 0x8000 }, + { CONFIG_TPM_TIS_BASE_ADDRESS, 0x8000 }, { 0, 0 } };