Elyes Haouas has submitted this change. ( https://review.coreboot.org/c/coreboot/+/86021?usp=email )
Change subject: tree: Use boolean for usb_phy_custom ......................................................................
tree: Use boolean for usb_phy_custom
Change-Id: I96decb66d632be874e517ffe1c842cd6124529b1 Signed-off-by: Elyes Haouas ehaouas@noos.fr Reviewed-on: https://review.coreboot.org/c/coreboot/+/86021 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Felix Held felix-coreboot@felixheld.de --- M src/mainboard/amd/birman/devicetree_glinda.cb M src/mainboard/amd/birman/devicetree_phoenix_fsp.cb M src/mainboard/amd/birman/devicetree_phoenix_opensil.cb M src/mainboard/amd/birman_plus/devicetree_glinda.cb M src/mainboard/amd/birman_plus/devicetree_phoenix.cb M src/mainboard/amd/chausie/devicetree.cb M src/mainboard/amd/mayan/devicetree_phoenix.cb M src/mainboard/google/guybrush/variants/baseboard/devicetree.cb M src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb M src/mainboard/google/myst/variants/baseboard/devicetree.cb M src/soc/amd/cezanne/chip.h M src/soc/amd/glinda/chip.h M src/soc/amd/mendocino/chip.h M src/soc/amd/phoenix/chip.h 14 files changed, 14 insertions(+), 14 deletions(-)
Approvals: build bot (Jenkins): Verified Felix Held: Looks good to me, approved
diff --git a/src/mainboard/amd/birman/devicetree_glinda.cb b/src/mainboard/amd/birman/devicetree_glinda.cb index cae73aa..f05a023 100644 --- a/src/mainboard/amd/birman/devicetree_glinda.cb +++ b/src/mainboard/amd/birman/devicetree_glinda.cb @@ -41,7 +41,7 @@
register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
- register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb b/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb index 3fc1f0d..ba18fc5 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_fsp.cb @@ -41,7 +41,7 @@
register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
- register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb index d84a010..9916931 100644 --- a/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb +++ b/src/mainboard/amd/birman/devicetree_phoenix_opensil.cb @@ -41,7 +41,7 @@
register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
- register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/birman_plus/devicetree_glinda.cb b/src/mainboard/amd/birman_plus/devicetree_glinda.cb index 5e92001..5a7fd00 100644 --- a/src/mainboard/amd/birman_plus/devicetree_glinda.cb +++ b/src/mainboard/amd/birman_plus/devicetree_glinda.cb @@ -41,7 +41,7 @@
register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
- register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/birman_plus/devicetree_phoenix.cb b/src/mainboard/amd/birman_plus/devicetree_phoenix.cb index afd4ca7..2490c9b 100644 --- a/src/mainboard/amd/birman_plus/devicetree_phoenix.cb +++ b/src/mainboard/amd/birman_plus/devicetree_phoenix.cb @@ -41,7 +41,7 @@
register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
- register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x1, diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index a186b2d..9077372 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -39,7 +39,7 @@
register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
- register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/mainboard/amd/mayan/devicetree_phoenix.cb b/src/mainboard/amd/mayan/devicetree_phoenix.cb index 898a592..bd6aeb4 100644 --- a/src/mainboard/amd/mayan/devicetree_phoenix.cb +++ b/src/mainboard/amd/mayan/devicetree_phoenix.cb @@ -41,7 +41,7 @@
register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO: reenable when PSPP works
- register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb index 2fe3e46..b58dc2c 100644 --- a/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/guybrush/variants/baseboard/devicetree.cb @@ -98,7 +98,7 @@
register "pspp_policy" = "DXIO_PSPP_BALANCED"
- register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ /* Left USB C0 Port */ .Usb2PhyPort[0] = { diff --git a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb index f221adc..02444aa 100644 --- a/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb +++ b/src/mainboard/google/guybrush/variants/nipperkin/overridetree.cb @@ -28,7 +28,7 @@
chip soc/amd/cezanne
- register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ /* Left USB C0 Port */ .Usb2PhyPort[0] = { diff --git a/src/mainboard/google/myst/variants/baseboard/devicetree.cb b/src/mainboard/google/myst/variants/baseboard/devicetree.cb index 62e19bf..97994c7 100644 --- a/src/mainboard/google/myst/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/myst/variants/baseboard/devicetree.cb @@ -85,7 +85,7 @@ register "pspp_policy" = "DXIO_PSPP_DISABLED" # TODO(b/277214353): reenable when PSPP works register "s0ix_enable" = "true"
- register "usb_phy_custom" = "1" + register "usb_phy_custom" = "true" register "usb_phy" = "{ .Usb2PhyPort[0] = { .compdistune = 0x3, diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index 738282f..bdf6ba8 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -93,7 +93,7 @@ DXIO_PSPP_POWERSAVE, } pspp_policy;
- uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy;
/* eDP phy tuning settings */ diff --git a/src/soc/amd/glinda/chip.h b/src/soc/amd/glinda/chip.h index 085bac5..186591f 100644 --- a/src/soc/amd/glinda/chip.h +++ b/src/soc/amd/glinda/chip.h @@ -103,7 +103,7 @@ DXIO_PSPP_POWERSAVE, } pspp_policy;
- uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy; };
diff --git a/src/soc/amd/mendocino/chip.h b/src/soc/amd/mendocino/chip.h index f161038..9a805b9 100644 --- a/src/soc/amd/mendocino/chip.h +++ b/src/soc/amd/mendocino/chip.h @@ -168,7 +168,7 @@ DXIO_PSPP_POWERSAVE, } pspp_policy;
- uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy; /* Set for PCIe optimization w/a and a double confirming on the result of PCIe Signal Integrity is highly recommended. */ diff --git a/src/soc/amd/phoenix/chip.h b/src/soc/amd/phoenix/chip.h index 07b0dab..eabd445 100644 --- a/src/soc/amd/phoenix/chip.h +++ b/src/soc/amd/phoenix/chip.h @@ -107,7 +107,7 @@ DXIO_PSPP_POWERSAVE, } pspp_policy;
- uint8_t usb_phy_custom; + bool usb_phy_custom; struct usb_phy_config usb_phy;
#if !CONFIG(PLATFORM_USES_FSP2_0)