Attention is currently required from: Karthik Ramasubramanian.
Raul Rangel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/52801 )
Change subject: mb/google/guybrush: Fix S0i3/S3 GPIO configuration
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Patch Set 3:
(1 comment)
File src/mainboard/google/guybrush/variants/baseboard/gpio.c:
https://review.coreboot.org/c/coreboot/+/52801/comment/f272da22_50ab91e7
PS3, Line 40: SOC_SAR_INT_L
Aah. I don't really see that as a wake requirement in go/cros-partner-docs though. […]
I'm not sure... I'll post on the bug. Thanks for raising this.
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