[coreboot-gerrit] [S] Change in coreboot[main]: WIP: simple, dumb, illegal instruction handling

[ron minnich (Code Review)]

Attention is currently required from: Philipp Hug.

ron minnich has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/81306?usp=email )

Change subject: WIP: simple, dumb, illegal instruction handling
......................................................................

WIP: simple, dumb, illegal instruction handling

This is a very simple example of an illegal instruction handler.

coreboot SBI is designed to minimize SBI functionality.
This minimization is reflected in the lack of generality
in the code. The ill() function switches out on a subset
of instrution types, because C compilers tend to use a
very limited subset of the possibilities of an instruction.

In this case, code will support only two illegal
instructions:
csrrs x10, time, x0
csrrs x14, time, x0

On modern RISC-V systems, the trap will not even occur. At some point RISC-V
community figured out that trapping on reading time was not always the best
idea :-)

So, in general, on future systems, reads will not trap.

This CL can not go in until Hug's menvcfg support goes in.

Signed-off-by: Ronald G Minnich

Change-Id: I2d7b610698eca01b19a996bc80b0b08af4aed078
---
M src/arch/riscv/trap_handler.c
M src/arch/riscv/virtual_memory.c
M util/scripts/prepare-commit-msg.clang-format
3 files changed, 12 insertions(+), 20 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/81306/1

diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c
index d66bed5..8bcb0968 100644
--- a/src/arch/riscv/trap_handler.c
+++ b/src/arch/riscv/trap_handler.c
@@ -132,16 +132,16 @@
    int insn_size = 4;

switch (insn) {
-		case 0xc0102773: // csrrs x14, time, x0
-			tf->gpr[24] = *HLS()->time;
-			break;
-		case 0xc0102573: // csrrs x10, time, x0
-			tf->gpr[20] = *HLS()->time;
-			break;
-		default: // proceed anyway.
-			printk(BIOS_EMERG, "Unhandled instruction: %x\n", insn);
-			print_trap_information(tf);
-			break;
+	case 0xc0102773: // csrrs x14, time, x0
+		tf->gpr[24] = *HLS()->time;
+		break;
+	case 0xc0102573: // csrrs x10, time, x0
+		tf->gpr[20] = *HLS()->time;
+		break;
+	default: // proceed anyway.
+		printk(BIOS_EMERG, "Unhandled instruction: %x\n", insn);
+		print_trap_information(tf);
+		break;
    }
    write_csr(mepc, read_csr(mepc) + insn_size);
 }
@@ -157,7 +157,6 @@
    case CAUSE_ILLEGAL_INSTRUCTION:
    	ill(tf);
    	return;
-		break;
    case CAUSE_MISALIGNED_FETCH:
    case CAUSE_FETCH_ACCESS:
    case CAUSE_BREAKPOINT:
diff --git a/src/arch/riscv/virtual_memory.c b/src/arch/riscv/virtual_memory.c
index 913836f..6ff2171 100644
--- a/src/arch/riscv/virtual_memory.c
+++ b/src/arch/riscv/virtual_memory.c
@@ -45,7 +45,8 @@
    // Delegate supervisor timer and other interrupts to supervisor mode,
    // if supervisor mode is supported.
    if (supports_extension('S')) {
-		if (ENV_RAMSTAGE && has_menvcfg)
+		/* this code depends on a later CL from Hug that adds menvcfg support. */
+		if (0 && ENV_RAMSTAGE && has_menvcfg)
    		delegate |= (1 << CAUSE_ILLEGAL_INSTRUCTION);
    	set_csr(mideleg, MIP_STIP | MIP_SSIP);
    	set_csr(medeleg, delegate);
diff --git a/util/scripts/prepare-commit-msg.clang-format b/util/scripts/prepare-commit-msg.clang-format
index a6b3d08..e1add3f 100755
--- a/util/scripts/prepare-commit-msg.clang-format
+++ b/util/scripts/prepare-commit-msg.clang-format
@@ -3,11 +3,3 @@
 if [ -z "$files" ]; then
    exit 0
 fi
-# This has to be set here; otherwise a grep error seems to cause
-# us to exit with non-zero status.
-set -e
-clang-format -i $files
-git add $files
-u=`git config user.name`
-m="clang-formatted-by: $u"
-echo $m >> $1