Felix Singer has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79939?usp=email )
Change subject: mb/lenovo/x220: Convert remaining PCI numbers into reference names ......................................................................
mb/lenovo/x220: Convert remaining PCI numbers into reference names
Change-Id: Ife8f3bc8b7fd14bb9a0e8dd4bc3d33b44c8f794f Signed-off-by: Felix Singer felixsinger@posteo.net Reviewed-on: https://review.coreboot.org/c/coreboot/+/79939 Tested-by: build bot (Jenkins) no-reply@coreboot.org Reviewed-by: Patrick Rudolph patrick.rudolph@9elements.com --- M src/mainboard/lenovo/x220/variants/x1/overridetree.cb M src/mainboard/lenovo/x220/variants/x220/overridetree.cb 2 files changed, 5 insertions(+), 5 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Rudolph: Looks good to me, approved
diff --git a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb index d236139..2defac8 100644 --- a/src/mainboard/lenovo/x220/variants/x1/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x1/overridetree.cb @@ -21,10 +21,10 @@ # X1 does not have ExpressCard slot register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
- device pci 1c.0 off end # PCIe Port #1 - device pci 1c.2 off end # PCIe Port #3 - device pci 1c.3 off end # PCIe Port #4 - device pci 1f.0 on #LPC bridge + device ref pcie_rp1 off end # PCIe Port #1 + device ref pcie_rp3 off end # PCIe Port #3 + device ref pcie_rp4 off end # PCIe Port #4 + device ref lpc on #LPC bridge chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "config2" = "0xe0" diff --git a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb index 8e939fd..9325480 100644 --- a/src/mainboard/lenovo/x220/variants/x220/overridetree.cb +++ b/src/mainboard/lenovo/x220/variants/x220/overridetree.cb @@ -1,7 +1,7 @@ chip northbridge/intel/sandybridge device domain 0 on chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH - device pci 1f.0 on #LPC bridge + device ref lpc on #LPC bridge chip ec/lenovo/h8 device pnp ff.2 on end # dummy register "eventa_enable" = "0x01"