[coreboot-gerrit] Change in coreboot[master]: soc/intel/tigerlake: Enable SATA

[Subrata Banik (Code Review)]

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38504 )

Change subject: soc/intel/tigerlake: Enable SATA
......................................................................

soc/intel/tigerlake: Enable SATA

Configure SATA FSP UPD according to mainboard design.

BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board with SATA memory

Signed-off-by: Wonkyu Kim 
Change-Id: I9350d71d76cd3d449fd959b5398d5ac653bc459e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38504
Reviewed-by: Nick Vaccaro 
Reviewed-by: Subrata Banik 
Tested-by: build bot (Jenkins) 
---
M src/soc/intel/tigerlake/fsp_params_tgl.c
1 file changed, 14 insertions(+), 0 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Subrata Banik: Looks good to me, approved
  Nick Vaccaro: Looks good to me, approved
  Wonkyu Kim: Looks good to me, but someone else must approve

diff --git a/src/soc/intel/tigerlake/fsp_params_tgl.c b/src/soc/intel/tigerlake/fsp_params_tgl.c
index fe59ac1..305748e 100644
--- a/src/soc/intel/tigerlake/fsp_params_tgl.c
+++ b/src/soc/intel/tigerlake/fsp_params_tgl.c
@@ -121,6 +121,20 @@
    /* PCH UART selection for FSP Debug */
    params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;

+	/* SATA */
+	dev = pcidev_on_root(PCH_DEV_SLOT_SATA, 0);
+	if (!dev)
+		params->SataEnable = 0;
+	else {
+		params->SataEnable = dev->enabled;
+		params->SataMode = config->SataMode;
+		params->SataSalpSupport = config->SataSalpSupport;
+		memcpy(params->SataPortsEnable, config->SataPortsEnable,
+			sizeof(params->SataPortsEnable));
+		memcpy(params->SataPortsDevSlp, config->SataPortsDevSlp,
+			sizeof(params->SataPortsDevSlp));
+	}
+
    mainboard_silicon_init_params(params);
 }