[coreboot-gerrit] Change in coreboot[master]: soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot

[Patrick Georgi (Code Review)]

Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/35170 )

Change subject: soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot
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soc/skylake: Write the P2SB IBDF and HBDF registers in coreboot

Do it in coreboot code instead of letting FSP do it.

Change-Id: Ic5e8a62141608463ade398432253bad460a9a79d
Signed-off-by: Angel Pons 
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35170
Tested-by: build bot (Jenkins) 
Reviewed-by: Michael Niewöhner
Reviewed-by: Nico Huber 
---
M src/soc/intel/skylake/chip.c
M src/soc/intel/skylake/include/soc/systemagent.h
M src/soc/intel/skylake/romstage/romstage.c
M src/soc/intel/skylake/romstage/systemagent.c
4 files changed, 13 insertions(+), 11 deletions(-)

Approvals:
  build bot (Jenkins): Verified
  Nico Huber: Looks good to me, but someone else must approve
  Michael Niewöhner: Looks good to me, approved

diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c
index 1e0803c..de11a9e 100644
--- a/src/soc/intel/skylake/chip.c
+++ b/src/soc/intel/skylake/chip.c
@@ -391,17 +391,15 @@
    /* Set TccActivationOffset */
    tconfig->TccActivationOffset = config->tcc_offset;

+	/* Already handled in coreboot code, so tell FSP to ignore UPDs */
+	params->PchIoApicBdfValid = 0;
+
    /* Enable VT-d and X2APIC */
    if (!config->ignore_vtd && soc_is_vtd_capable()) {
    	params->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS;
    	params->VtdBaseAddress[1] = VTVC0_BASE_ADDRESS;
    	params->X2ApicOptOut = 0;
    	tconfig->VtdDisable = 0;
-
-		params->PchIoApicBdfValid = 1;
-		params->PchIoApicBusNumber = V_P2SB_IBDF_BUS;
-		params->PchIoApicDeviceNumber = V_P2SB_IBDF_DEV;
-		params->PchIoApicFunctionNumber = V_P2SB_IBDF_FUN;
    }

dev = pcidev_path_on_root(SA_DEVFN_IGD);
diff --git a/src/soc/intel/skylake/include/soc/systemagent.h b/src/soc/intel/skylake/include/soc/systemagent.h
index 565c885..91209c8 100644
--- a/src/soc/intel/skylake/include/soc/systemagent.h
+++ b/src/soc/intel/skylake/include/soc/systemagent.h
@@ -66,9 +66,11 @@
 #define V_P2SB_IBDF_BUS	250
 #define V_P2SB_IBDF_DEV	31
 #define V_P2SB_IBDF_FUN	0
+#define V_DEFAULT_IBDF	((V_P2SB_IBDF_BUS << 8) | PCI_DEVFN(V_P2SB_IBDF_DEV, V_P2SB_IBDF_FUN))

#define V_P2SB_HBDF_BUS	250
 #define V_P2SB_HBDF_DEV	15
 #define V_P2SB_HBDF_FUN	0
+#define V_DEFAULT_HBDF	((V_P2SB_HBDF_BUS << 8) | PCI_DEVFN(V_P2SB_HBDF_DEV, V_P2SB_HBDF_FUN))

#endif
diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c
index 2904f05..d381caa 100644
--- a/src/soc/intel/skylake/romstage/romstage.c
+++ b/src/soc/intel/skylake/romstage/romstage.c
@@ -248,12 +248,9 @@

cpu_flex_override(m_cfg);

-	if (!config->ignore_vtd) {
-		m_cfg->PchHpetBdfValid = 1;
-		m_cfg->PchHpetBusNumber = V_P2SB_HBDF_BUS;
-		m_cfg->PchHpetDeviceNumber = V_P2SB_HBDF_DEV;
-		m_cfg->PchHpetFunctionNumber = V_P2SB_HBDF_FUN;
-	}
+	/* HPET BDF already handled in coreboot code, so tell FSP to ignore UPDs */
+	m_cfg->PchHpetBdfValid = 0;
+
    m_cfg->HyperThreading = CONFIG(FSP_HYPERTHREADING);
 }

diff --git a/src/soc/intel/skylake/romstage/systemagent.c b/src/soc/intel/skylake/romstage/systemagent.c
index bf0d506..e1272a1 100644
--- a/src/soc/intel/skylake/romstage/systemagent.c
+++ b/src/soc/intel/skylake/romstage/systemagent.c
@@ -19,6 +19,7 @@
 #include <device/pci_ops.h>
 #include <intelblocks/systemagent.h>
 #include <soc/iomap.h>
+#include <soc/p2sb.h>
 #include <soc/pci_devs.h>
 #include <soc/romstage.h>
 #include <soc/systemagent.h>
@@ -38,6 +39,10 @@
    if (!vtd_capable)
    	return;

+	/* Configure P2SB VT-d originators (HPET and IOAPIC) */
+	pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_HBDF, V_DEFAULT_HBDF);
+	pci_write_config16(PCH_DEV_P2SB, PCH_P2SB_IBDF, V_DEFAULT_IBDF);
+
    if (igd_dev && igd_dev->enabled)
    	sa_set_mch_bar(&soc_gfxvt_mmio_descriptor, 1);