[coreboot-gerrit] Change in coreboot[master]: soc/intel/cannonlake: Check for supported UART index

[Subrata Banik (Code Review)]

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/20999

Change subject: soc/intel/cannonlake: Check for supported UART index
......................................................................

soc/intel/cannonlake: Check for supported UART index

if UART index is 2 then Base address for LPSS UART2 is selected
else assert because cannonlake chrome design don't support legacy UART
selection.

Change-Id: I31b239e7e6b7e9ac8ea2fcfbcbd8cb148ef9e586
Signed-off-by: Subrata Banik 
---
M src/soc/intel/cannonlake/uart.c
1 file changed, 6 insertions(+), 0 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/20999/1

diff --git a/src/soc/intel/cannonlake/uart.c b/src/soc/intel/cannonlake/uart.c
index 38f499d..ce1241f 100644
--- a/src/soc/intel/cannonlake/uart.c
+++ b/src/soc/intel/cannonlake/uart.c
@@ -14,6 +14,7 @@
  */

#include <assert.h>
+#include <console/console.h>
 #include <console/uart.h>
 #include <device/pci_def.h>
 #include <intelblocks/gpio.h>
@@ -79,6 +80,11 @@

uintptr_t uart_platform_base(int idx)
 {
+	/* Same base address for all debug port usage. In reality UART2
+	 * is currently only supported. */
+	if (idx != 2)
+		die("unsupported UART index");
+
    /* We can only have one serial console at a time */
    return UART_DEBUG_BASE_ADDRESS;
 }