Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/31386 )
Change subject: soc/amd/stoneyridge/southbridge.c: Add new source to sb_clk_output_48Mhz ......................................................................
Patch Set 1:
(2 comments)
https://review.coreboot.org/#/c/31386/1//COMMIT_MSG Commit Message:
https://review.coreboot.org/#/c/31386/1//COMMIT_MSG@9 PS1, Line 9: In preparation for board padmelon which will use a clock source different : from the one already present in sb_clk_output_48Mhz, change its code to : input the desired clock source and set appropriate register based on this : input. I wouldn't bother with mentioning prep for Padmelon. You're adding support for existing Stoney Ridge functionality. Also, it's not a clock source or input. It's an oscillator out.
The original patch's commit message said:
soc/amd/stoneyridge: Expand 48MHz for both osc out signals
There are typically two configurable oscillator outputs available on APUs or FCHs. Convert the enable function to all either one.
https://review.coreboot.org/#/c/31386/1/src/soc/amd/stoneyridge/southbridge.... File src/soc/amd/stoneyridge/southbridge.c:
https://review.coreboot.org/#/c/31386/1/src/soc/amd/stoneyridge/southbridge.... PS1, Line 398: /* : * Enable the X14M_25M_48M_OSC pin and leaving it at it's default so : * 48Mhz will be on ball AP13 (FT3b package) : */ The original work this patch is based on changed this comment to say something like, "Clear the disable for OSCOUT1 (signal typically named XnnM_25M_48M) or OSCOUT2 (USBCLK/25M_48M_OSC). The frequency defaults to 48MHz." We shouldn't mention the package at all; FT3b and ball AP13 shouldn't have made their way into the original ST port.