[coreboot-gerrit] Change in coreboot[master]: intel/i945: Delay bridge VGA IO enable to ramstage

[Kyösti Mälkki (Code Review)]

Kyösti Mälkki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/35676 )

Change subject: intel/i945: Delay bridge VGA IO enable to ramstage
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intel/i945: Delay bridge VGA IO enable to ramstage

Change-Id: Ifc54ecc96b6d9d79d5a16b2d7baeae70b59275c9
Signed-off-by: Kyösti Mälkki 
---
M src/northbridge/intel/i945/early_init.c
1 file changed, 0 insertions(+), 5 deletions(-)

git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/35676/1

diff --git a/src/northbridge/intel/i945/early_init.c b/src/northbridge/intel/i945/early_init.c
index 791baec..c53577b 100644
--- a/src/northbridge/intel/i945/early_init.c
+++ b/src/northbridge/intel/i945/early_init.c
@@ -661,11 +661,6 @@
    	reg32 = pci_read_config32(PCI_DEV(0, 0x0, 0), DEVEN);
    	reg32 &= ~(DEVEN_D2F0 | DEVEN_D2F1);
    	pci_write_config32(PCI_DEV(0, 0x0, 0), DEVEN, reg32);
-
-		/* Set VGA enable bit in PCIe bridge */
-		reg16 = pci_read_config16(p2peg, PCI_BRIDGE_CONTROL);
-		reg16 |= PCI_BRIDGE_CTL_VGA;
-		pci_write_config16(p2peg, PCI_BRIDGE_CONTROL, reg16);
    }

/* Enable GPEs */