Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/37305 )
Change subject: sc7180: clock: Add support for QUP DFSR configuration ......................................................................
Patch Set 1: Code-Review+2
(2 comments)
https://review.coreboot.org/c/coreboot/+/37305/1/src/soc/qualcomm/sc7180/clo... File src/soc/qualcomm/sc7180/clock.c:
https://review.coreboot.org/c/coreboot/+/37305/1/src/soc/qualcomm/sc7180/clo... PS1, Line 231: void clock_configure_dfsr(int qup)
This would be invoked by the QUPv3 firmware driver to enable the QUPv3 SE clocks to dynamic frequency switch mode. The firmware driver is aware of which SEs to be kept in the DFS mode.
How are we aware of that? Is it just based on type (e.g. all SPI and all I2C)? Or do we need to hardcode it for every QUP?
https://review.coreboot.org/c/coreboot/+/37305/1/src/soc/qualcomm/sc7180/clo... PS1, Line 233: int idx, s = qup % QUP_WRAP1_S0; nit: please write
int idx; int s = qup % QUP_WRAP1_S0;
for clarity.