Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Patrick Rudolph, Tim Chu.
Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85806?usp=email )
Change subject: cpu/x86/64bit: Install extended page tables in BSS ......................................................................
Patch Set 3: Code-Review+1
(4 comments)
File src/cpu/x86/64bit/mmu.c:
https://review.coreboot.org/c/coreboot/+/85806/comment/aea22df5_c0b7235f?usp... : PS3, Line 49: * when 1GB PT aren't supported it maps 40 bits of the address space (512GiB). IMO the x86_64 by default boot with 4-level paging and here the 40bit VA is mainly for consideration of page table size, right?
https://review.coreboot.org/c/coreboot/+/85806/comment/c804c538_b211ecf2?usp... : PS3, Line 61: Not sure if macros could be used to represent the constants, e.g. 512ULL, as (1 << PDPT_BITS)?
https://review.coreboot.org/c/coreboot/+/85806/comment/e03e2b85_2c85803f?usp... : PS3, Line 157: */ It would be helpful if we could have comments here as well, e.g.
When 1GB PT are supported it maps 48 bits (the maximum 4-LVL paging supports), when 1GB PT aren't supported it maps 40 bits of the address space (512GiB).
https://review.coreboot.org/c/coreboot/+/85806/comment/c29e7fe1_89a0d1b6?usp... : PS3, Line 160: /* Using 512 4K pages limits the usable address space */ Do we need to make sure the CPU is not working under 5-level paging? (though coreboot never enables it).