Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/82148?usp=email )
Change subject: arch/x86: Include page tables in each stage ......................................................................
arch/x86: Include page tables in each stage
Change-Id: Iefe0429db7d6ef5c434beffd39aacaf7a72ce244 Signed-off-by: Arthur Heymans arthur@aheymans.xyz --- M src/arch/x86/assembly_entry.S M src/arch/x86/c_start.S 2 files changed, 7 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/82148/1
diff --git a/src/arch/x86/assembly_entry.S b/src/arch/x86/assembly_entry.S index 7f19e21..6e921ae 100644 --- a/src/arch/x86/assembly_entry.S +++ b/src/arch/x86/assembly_entry.S @@ -26,6 +26,10 @@ /* Migrate GDT to this text segment */ #if ENV_X86_64 call gdt_init64 +#if !CONFIG(PAGE_TABLES_IN_CBFS) + movq $PM4LE, %rax + movq %rax, %cr3 +#endif #else call gdt_init #endif diff --git a/src/arch/x86/c_start.S b/src/arch/x86/c_start.S index 94b9bd9..150196e 100644 --- a/src/arch/x86/c_start.S +++ b/src/arch/x86/c_start.S @@ -28,6 +28,9 @@ #if ENV_X86_64 movabs $gdtaddr, %rax lgdt (%rax) + + movq $PM4LE, %rax + movq %rax, %cr3 #else lgdt %cs:gdtaddr ljmp $RAM_CODE_SEG, $1f