[coreboot-gerrit] Patch merged into coreboot/master: nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform level

the following patch was just integrated into master:
commit c5c3d76127c0a3766f9f37710a4b6756e16497de
Author: Timothy Pearson 
Date:   Wed Apr 6 16:10:38 2016 -0500

nb/amd/mct_ddr3: Cache whether ECC is allowed at the platform level

Certain AMD platforms, such as those using the SP5100 southbridge,
    contain a very poorly documented bug related to LPC ROM access,
    which is triggered by repeated (hundreds or more) rapid calls to
    get_option().  This bug manifests as a complete system deadlock
    in ramstage device configuration, requiring standby power to be
    removed from the system to release the deadlock.

Cache the platform ECC status to avoid repeated calls to get_option()
    in the lane count detection logic.

Change-Id: I8b48c523218ccc8c113319957d6eca2d15e1070f
    Signed-off-by: Timothy Pearson 
    Reviewed-on: https://review.coreboot.org/14273
    Tested-by: build bot (Jenkins)
    Tested-by: Raptor Engineering Automated Test Stand 
    Reviewed-by: Felix Held 
    Reviewed-by: Paul Menzel 
    Reviewed-by: Martin Roth

See https://review.coreboot.org/14273 for details.

-gerrit