Patrick Georgi has submitted this change. ( https://review.coreboot.org/c/coreboot/+/38874 )
Change subject: mb/jetway/nf81-t56n-lf: Switch away from ROMCC_BOOTBLOCK ......................................................................
mb/jetway/nf81-t56n-lf: Switch away from ROMCC_BOOTBLOCK
Warning: Not tested on hardware.
Signed-off-by: Elyes HAOUAS ehaouas@noos.fr Signed-off-by: Mike Banon mikebdp2@gmail.com Change-Id: I2ccdb10b7e06e4c159b5a0203131f6ac4c37aacf Reviewed-on: https://review.coreboot.org/c/coreboot/+/38874 Reviewed-by: Patrick Georgi pgeorgi@google.com Tested-by: build bot (Jenkins) no-reply@coreboot.org --- M src/mainboard/jetway/nf81-t56n-lf/Kconfig M src/mainboard/jetway/nf81-t56n-lf/Kconfig.name M src/mainboard/jetway/nf81-t56n-lf/Makefile.inc R src/mainboard/jetway/nf81-t56n-lf/bootblock.c 4 files changed, 6 insertions(+), 10 deletions(-)
Approvals: build bot (Jenkins): Verified Patrick Georgi: Looks good to me, approved HAOUAS Elyes: Looks good to me, but someone else must approve
diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig b/src/mainboard/jetway/nf81-t56n-lf/Kconfig index dfa01b9..d2dda67 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig @@ -14,14 +14,10 @@ # GNU General Public License for more details. #
-config BOARD_JETWAY_NF81_T56N_LF - def_bool n - if BOARD_JETWAY_NF81_T56N_LF
config BOARD_SPECIFIC_OPTIONS def_bool y - #select ROMCC_BOOTBLOCK select CPU_AMD_AGESA_FAMILY14 select NORTHBRIDGE_AMD_AGESA_FAMILY14 select SOUTHBRIDGE_AMD_CIMX_SB800 diff --git a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name index 0b67627..2e660f9 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name +++ b/src/mainboard/jetway/nf81-t56n-lf/Kconfig.name @@ -1,2 +1,2 @@ -#config BOARD_JETWAY_NF81_T56N_LF -# bool"NF81_T56N_LF" +config BOARD_JETWAY_NF81_T56N_LF + bool "NF81_T56N_LF" diff --git a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc index ba56286..bf86007 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc +++ b/src/mainboard/jetway/nf81-t56n-lf/Makefile.inc @@ -20,6 +20,8 @@ pci$(stripped_ahcibios_id).rom-type := optionrom endif
+bootblock-y += bootblock.c + romstage-y += buildOpts.c romstage-y += BiosCallOuts.c romstage-y += OemCustomize.c diff --git a/src/mainboard/jetway/nf81-t56n-lf/romstage.c b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c similarity index 87% rename from src/mainboard/jetway/nf81-t56n-lf/romstage.c rename to src/mainboard/jetway/nf81-t56n-lf/bootblock.c index 5e61bdd..5ecfaf7 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/romstage.c +++ b/src/mainboard/jetway/nf81-t56n-lf/bootblock.c @@ -14,16 +14,14 @@ * GNU General Public License for more details. */
-#include <northbridge/amd/agesa/state_machine.h> +#include <bootblock_common.h> #include <superio/fintek/common/fintek.h> #include <superio/fintek/f71869ad/f71869ad.h> -#include <sb_cimx.h>
/* Ensure Super I/O config address (i.e., 0x2e or 0x4e) matches that of devicetree.cb */ #define SERIAL_DEV PNP_DEV(0x2e, F71869AD_SP1)
-void board_BeforeAgesa(struct sysinfo *cb) +void bootblock_mainboard_early_init(void) { - sb_Poweron_Init(); fintek_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); }